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56 lines
1.5 KiB
Plaintext
56 lines
1.5 KiB
Plaintext
SD Flash interface
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regsiter map:
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1. clock divider
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2. address
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3. data register
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4. command register
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5. size register
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Number of bytes to read or write.
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6. status register
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1. bits 11 to 0: bytes currently in the buffer
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2. bits 12 to 29: reservered
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3. bit 30: fault
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4. bit 31: busy
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5. bits XLEN-1 to 32: reservered
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non dma read operation
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1. write the address regsiter
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2. write the command register to read
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3. wait for interrupt or pool on status
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4. Check status for fault and number of bytes.
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5. read the data register for 512 bytes. (64 ld, or 128 lw)
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non dma write operation
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1. write address register
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2. write data register for 512 bytes. (64 sd, or 128 sw)
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3. write command register to write data to flash
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4. wait for interrupt or pool on status
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5. check status for fault and number of bytes written.
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implement dma transfers later
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interrupts
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1. operation done
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2. bus error (more of an exception)
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Occurs if attempting to do an operation while the flash controller is busy.
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ie. if status[31] is set generate an interrupt
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This is tricky in a multiprocessor environment.
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tasks
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1. [-] Remove all AFRL identifiers
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2. [X] get the existing sdc compiled on wally.
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1. [X] use wally primatives over tcore's
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3. build abhlite interface with the above registers and necessary fsm.
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1. [ ] The sd card reader uses a 4 bit data interface. We can change this to be something
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more pratical.
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4. write test programs
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5. [X] Convert VHDL to system verilog
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