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cvw/wally-pipelined/src
History
bbracker 58d0e46d02 UART improved and added more reg read side effects
2021-06-10 09:53:48 -04:00
..
cache Continued I-Cache cleanup. 2021-06-04 15:14:05 -05:00
dmem Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
ebu Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
fpu lint is clean 2021-06-07 14:22:54 -04:00
generic fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
hazard lint is clean 2021-06-07 14:22:54 -04:00
ieu fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
ifu Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
mmu Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
muldiv lint is clean 2021-06-07 14:22:54 -04:00
privileged Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
uncore UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00
wally Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00