mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
372 lines
8.6 KiB
Python
Executable File
372 lines
8.6 KiB
Python
Executable File
#!/usr/bin/env python3
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##################################
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# testgen-CAUSE.py
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#
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# dottolia@hmc.edu 27 Apr 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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#
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#
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##################################
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# DOCUMENTATION:
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# Most of the comments explaining what everything
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# does can be found in testgen-TVAL.py
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###################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# functions
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##################################
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#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
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def randRegs():
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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reg3 = randint(1,20)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return str(reg1), str(reg2), str(reg3)
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def writeVectors(storecmd):
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global testnum
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# User Software Interrupt: True, 0
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# Supervisor Software Interrupt: True, 1
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# Machine Software Interrupt: True, 2
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writeTest(storecmd, f, r, "timer-interrupt", True, -1) # code determined inside of writeTest
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# User external input: True, 8
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# Supervisor external input: True, 9
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# Machine externa input: True, 11
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# Instruction address misaligned: False, 0
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# Instruction access fault: False, 1
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# Illegal Instruction
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writeTest(storecmd, f, r, f"""
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.fill 1, 4, 0
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""", False, 2)
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# Breakpoint
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writeTest(storecmd, f, r, "ebreak", False, 3)
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# Load Address Misaligned
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writeTest(storecmd, f, r, f"""
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lw x0, 11(x0)
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""", False, 4)
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# # Load Access fault: False, 5
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# # Store/AMO address misaligned
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writeTest(storecmd, f, r, f"""
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sw x0, 11(x0)
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""", False, 6)
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# Breakpoint: codes 8, 9, 11
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writeTest(storecmd, f, r, "ecall", False, -1) # code determined inside of writeTest
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# Instruction page fault: 12
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Load page fault: 13
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Store/AMO page fault: 15
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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#writeTest(storecmd, f, r, "ecall", False, 11, "m")
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def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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global testnum
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global testMode
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global isInterrupts
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beforeTest = ""
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if interrupt != isInterrupts:
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return
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isTimerInterruptTest = test == "timer-interrupt"
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delegateType = "i" if interrupt else "e"
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for mode in (["m", "s", "u"] if testMode == "m" else ["s", "u"]):
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if isTimerInterruptTest:
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clintAddr = "0x2004000"
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if mode == "m":
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code = 7
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test = f"""
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la x18, {clintAddr}
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{storecmd} x0, 0(x18)
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"""
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elif mode == "s":
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code = 5
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test = ""
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else:
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code = 4
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test = ""
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ieMask = 1 << code
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statusMask = 0b1010
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beforeTest = f"""
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li x1, {statusMask}
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csrrs x0, mstatus, x1
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li x1, 0b0010
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csrrs x0, sstatus, x1
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la x18, {clintAddr}
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lw x11, 0(x18)
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li x1, 0x7fffffffffffffff
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{storecmd} x1, 0(x18)
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li x1, {ieMask}
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csrrs x0, mie, x1
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li x1, {ieMask}
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csrrs x0, sie, x1
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"""
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resetHander = f"""
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#li x1, 0x80
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#csrrc x0, sie, x1
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li x1, {ieMask}
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csrrc x0, mie, x1
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li x1, {ieMask}
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csrrc x0, sie, x1
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li x1, {statusMask}
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csrrc x0, mstatus, x1
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li x1, 0b0010
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csrrc x0, sstatus, x1
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la x18, {clintAddr}
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{storecmd} x11, 0(x18)
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"""
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if mode == "s":
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beforeTest += f"""
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li x1, {ieMask}
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csrrs x0, sip, x1
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"""
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resetHander += f"""
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li x1, {ieMask}
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csrrc x0, sip, x1
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"""
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elif test == "ecall":
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if mode == "m":
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code = 11
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elif mode == "s":
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code = 9
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else:
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code = 8
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mask = 1 << code
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for delegated in [True, False]:
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labelSuffix = testnum
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f.write(f"""
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_start_{labelSuffix}:
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la x1, _j_m_trap_{labelSuffix}
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csrw mtvec, x1
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la x1, _j_s_trap_{labelSuffix}
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csrw stvec, x1
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j _j_test_{labelSuffix}
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_j_m_trap_{labelSuffix}:
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{resetHander}
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li x25, 3
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csrr x1, mepc
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addi x1, x1, 4
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csrrw x0, mepc, x1
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bnez x30, _j_finished_{labelSuffix}
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mret
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_j_s_trap_{labelSuffix}:
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{resetHander}
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li x25, 1
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csrr x1, sepc
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addi x1, x1, 4
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csrrw x0, sepc, x1
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bnez x30, _j_goto_machine_mode_{labelSuffix}
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sret
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_j_goto_machine_mode_{labelSuffix}:
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li x30, 1
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{"ebreak" if test is not "ebreak" else "ecall"}
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_j_test_{labelSuffix}:
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""")
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original = f"""
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li x1, {mask if delegated else 0}
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csrw m{delegateType}deleg, x1
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"""
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if mode != "m":
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lines = f"""
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{original}
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{beforeTest}
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li x1, 0b110000000000
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csrrc x31, {testMode}status, x1
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li x1, 0b{"01" if mode == "s" else "00"}00000000000
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csrrs x31, {testMode}status, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the ret instruction
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csrrw x27, {testMode}epc, x1
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{testMode}ret
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# From {testMode}, we're now in {mode} mode...
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{test}
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"""
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writeTestInner(storecmd, f, r, lines, 1 if delegated else 3)
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f.write(f"""
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j _j_goto_machine_mode_{labelSuffix}
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""")
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else:
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lines = f"""
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{original}
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{beforeTest}
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{test}
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"""
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writeTestInner(storecmd, f, r, lines, 3)
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f.write(f"""
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_j_finished_{labelSuffix}:
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li x30, 0
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""")
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def writeTestInner(storecmd, f, r, lines, expected):
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global testnum
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lines = f"""
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li x25, 0xDEADBEA7
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{lines}
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"""
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lines += storecmd + " x25, " + str(testnum * wordsize) + "(x6)\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 1;
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# setup
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seed(0xD0C0_D0C0_D0C0_D0C0) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for testMode in ["m"]:
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for isInterrupts in [True, False]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + ("I" if isInterrupts else "E") + "DELEG"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# All registers used:
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: mideleg old value
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f.write(f"""
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add x7, x6, x0
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csrr x19, mtvec
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csrr x18, medeleg
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csrr x17, medeleg
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""")
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testnum = 0
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for i in range(0, 2):
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writeVectors(storecmd)
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f.write(f"""
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csrw mtvec, x19
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csrw medeleg, x18
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csrw mideleg, x17
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""")
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# if we're in supervisor mode, this leaves the ebreak instruction untested (we need a way to)
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# get back to machine mode.
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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