cvw/pipelined/src/generic
2022-09-07 11:36:35 -07:00
..
flop James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
mem Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
adder.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
aplusbeq0.sv Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
arrs.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
clockgater.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
counter.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
csa.sv moved CSA to generic 2022-08-22 08:41:23 +00:00
decoder.sv Fixed unpacking bug; regression runs again 2022-01-06 18:22:30 +00:00
lzc.sv removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
mux.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
neg.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
onehotdecoder.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
or_rows.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
priorityonehot.sv new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
prioritythermometer.sv Fixed unpacking bug; regression runs again 2022-01-06 18:22:30 +00:00