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318 lines
10 KiB
Systemverilog
318 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu 13 January 2022
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// Modified: cturek@hmc.edu June 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF) : 0)
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`define EXTRAINTBITS ((`NF<(`XLEN)) ? 0 : (`NF - `XLEN))
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module srt (
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input logic clk,
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input logic Start,
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input logic Stall, // *** multiple pipe stages
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input logic Flush, // *** multiple pipe stages
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// Floating Point Inputs
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// later add exponents, signs, special cases
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input logic XSign, YSign,
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input logic [`NE-1:0] XExp, YExp,
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input logic [`NF-1:0] SrcXFrac, SrcYFrac,
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic rsign, done,
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output logic [`DIVLEN-1:0] Rem, Quot, // *** later handle integers
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output logic [`NE-1:0] rExp,
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output logic [3:0] Flags
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);
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logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [`NE-1:0] calcExp;
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logic calcSign;
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logic [`DIVLEN+3:0] X, Dpreproc;
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logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [$clog2(`XLEN+1)-1:0] intExp, dur, calcDur;
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logic intSign;
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srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, XExp, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, calcDur, intSign);
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+2:0], 1'b0}, X, Start, WSN);
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flop #(`DIVLEN+4) wsflop(clk, WSN, WS);
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mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+2:0], 1'b0}, {(`DIVLEN+4){1'b0}}, Start, WCN);
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flop #(`DIVLEN+4) wcflop(clk, WCN, WC);
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flopen #(`DIVLEN+4) dflop(clk, Start, Dpreproc, D);
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qm);
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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flopen #(7) durflop(clk, Start, calcDur, dur);
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counter divcounter(clk, Start, dur, done);
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// Divisor Selection logic
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assign Db = ~D;
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mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
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// Partial Product Generation
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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expcalc expcalc(.XExp, .YExp, .calcExp);
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signcalc signcalc(.XSign, .YSign, .calcSign);
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endmodule
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////////////////
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// Submodules //
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////////////////
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///////////////////
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// Preprocessing //
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///////////////////
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module srtpreproc (
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [`NF-1:0] SrcXFrac, SrcYFrac,
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input logic [`NE-1:0] XExp,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [`DIVLEN+3:0] X, D,
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output logic [$clog2(`XLEN+1)-1:0] intExp, dur, // Quotient integer exponent
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output logic intSign // Quotient integer sign
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);
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logic [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB;
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logic [`XLEN-1:0] PosA, PosB;
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logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY, DivX, SqrtX;
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assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
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lzc #(`XLEN) lzcA (PosA, zeroCntA);
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lzc #(`XLEN) lzcB (PosB, zeroCntB);
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assign ExtraA = {PosA, {`EXTRAINTBITS{1'b0}}};
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assign ExtraB = {PosB, {`EXTRAINTBITS{1'b0}}};
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assign PreprocA = ExtraA << (zeroCntA + 1);
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assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}};
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assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}};
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assign DivX = Int ? PreprocA : PreprocX;
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assign SqrtX = {XExp[0] ? 4'b0000 : 4'b1111, SrcXFrac};
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assign X = Sqrt ? SqrtX : {4'b0001, DivX};
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assign D = {4'b0001, Int ? PreprocB : PreprocY};
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assign intExp = zeroCntB - zeroCntA + 1;
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assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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assign dur = Int ? (intExp & {7{~intExp[6]}}) : (`DIVLEN + 2);
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endmodule
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/////////////////////////////////
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// Quotient Selection, Radix 2 //
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/////////////////////////////////
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module qsel2 ( // *** eventually just change to 4 bits
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input logic [`DIVLEN+3:`DIVLEN] ps, pc,
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output logic qp, qz, qm
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);
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logic [`DIVLEN+3:`DIVLEN] p, g;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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// for efficiency. You can probably optimize your logic to
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// select the proper divisor with less delay.
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// Quotient equations from EE371 lecture notes 13-20
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]);
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assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & g[`DIVLEN]));
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assign #1 sign = p[`DIVLEN+3] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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assign #1 sign = (ps[55]^pc[55])^
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(ps[54] & pc[54] | ((ps[54]^pc[54]) &
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(ps[53]&pc[53] | ((ps[53]^pc[53]) &
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(ps[52]&pc[52]))))); */
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// Produce quotient = +1, 0, or -1
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assign #1 qp = magnitude & ~sign;
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assign #1 qz = ~magnitude;
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assign #1 qm = magnitude & sign;
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endmodule
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///////////////////////////////////
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// On-The-Fly Converter, Radix 2 //
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///////////////////////////////////
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module otfc2 #(parameter N=64) (
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input logic clk,
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input logic Start,
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input logic qp, qz, qm,
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output logic [N-1:0] r
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);
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// The on-the-fly converter transfers the quotient
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// bits to the quotient as they come.
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//
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// This code follows the psuedocode presented in the
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// floating point chapter of the book. Right now,
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// it is written for Radix-2 division.
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//
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// QM is Q-1. It allows us to write negative bits
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// without using a costly CPA.
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logic [N+2:0] Q, QM, QNext, QMNext, QMMux;
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// QR and QMR are the shifted versions of Q and QM.
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// They are treated as [N-1:r] size signals, and
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// discard the r most significant bits of Q and QM.
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logic [N+1:0] QR, QMR;
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flopr #(N+3) Qreg(clk, Start, QNext, Q);
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mux2 #(`DIVLEN+3) QMmux(QMNext, {`DIVLEN+3{1'b1}}, Start, QMMux);
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flop #(`DIVLEN+3) QMreg(clk, QMMux, QM);
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always_comb begin
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QR = Q[N+1:0];
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QMR = QM[N+1:0]; // Shift Q and QM
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if (qp) begin
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QNext = {QR, 1'b1};
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QMNext = {QR, 1'b0};
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end else if (qz) begin
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QNext = {QR, 1'b0};
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QMNext = {QMR, 1'b1};
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end else begin // If qp and qz are not true, then qm is
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QNext = {QMR, 1'b1};
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QMNext = {QMR, 1'b0};
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end
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end
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assign r = Q[N+2] ? Q[N+1:2] : Q[N:1];
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endmodule
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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input logic [$clog2(`XLEN+1)-1:0] dur,
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output logic done);
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logic [$clog2(`XLEN+1)-1:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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if (count == dur) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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//////////
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// mux3 //
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//////////
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module mux3onehot #(parameter N=65) (
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input logic [N+3:0] in0, in1, in2,
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input logic sel0, sel1, sel2,
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output logic [N+3:0] out
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);
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// lazy inspection of the selects
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// really we should make sure selects are mutually exclusive
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assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2);
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endmodule
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/////////
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// csa //
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/////////
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module csa #(parameter N=69) (
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input logic [N-1:0] in1, in2, in3,
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input logic cin,
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output logic [N-1:0] out1, out2
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);
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// This block adds in1, in2, in3, and cin to produce
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// a result out1 / out2 in carry-save redundant form.
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// cin is just added to the least significant bit and
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// is required to handle adding a negative divisor.
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// Fortunately, the carry (out2) is shifted left by one
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// bit, leaving room in the least significant bit to
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// insert cin.
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assign #1 out1 = in1 ^ in2 ^ in3;
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assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) |
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(in2[N-2:0] & in3[N-2:0]), cin};
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endmodule
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//////////////
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// expcalc //
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//////////////
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module expcalc(
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input logic [`NE-1:0] XExp, YExp,
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output logic [`NE-1:0] calcExp
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);
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assign calcExp = XExp - YExp + (`NE)'(`BIAS);
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endmodule
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//////////////
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// signcalc //
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//////////////
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module signcalc(
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input logic XSign, YSign,
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output logic calcSign
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);
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assign calcSign = XSign ^ YSign;
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endmodule |