mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
43 lines
2.2 KiB
Bash
Executable File
43 lines
2.2 KiB
Bash
Executable File
#!/bin/bash
|
|
# simulate with Verilator
|
|
|
|
export PATH=$PATH:/usr/local/bin/
|
|
verilator=`which verilator`
|
|
|
|
basepath=$(dirname $0)/..
|
|
#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
|
|
|
|
# define associateive array of tests to run
|
|
declare -A suites
|
|
rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv")
|
|
suites["rv64gc"]=${rv64gccases[@]}
|
|
rv64icases=("arch64i")
|
|
suites["rv64i"]=${rv32icases[@]}
|
|
rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv")
|
|
suites["rv32gc"]=${rv32gccases[@]}
|
|
rv32imccases=("arch32i" "arch32m" "arch32c")
|
|
suites["rv32imc"]=${rv32imccases[@]}
|
|
rv32icases=("arch32i")
|
|
suites["rv32i"]=${rv32icases[@]}
|
|
rv32ecases=("arch32e")
|
|
suites["rv32e"]=${rv32ecases[@]}
|
|
|
|
for config in ${!suites[@]}; do
|
|
for suite in ${suites[${config}]}; do
|
|
echo "Verilating ${config} ${suite}"
|
|
if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
|
echo "Exiting after ${config} ${suite} verilation due to errors or warnings"
|
|
exit 1
|
|
fi
|
|
./obj_dir/Vtestbench
|
|
done
|
|
done
|
|
echo "Verilation complete"
|
|
|
|
# command line to invoke Verilator on rv64gc arch64i
|
|
# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
|
|
|
|
# command line with debugging to address core dumps
|
|
# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
|
|
|