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104 lines
4.5 KiB
Systemverilog
104 lines
4.5 KiB
Systemverilog
///////////////////////////////////////////
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// csrn.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// dottolia@hmc.edu 3 May 2021 - fix bug with utvec getting wrong value
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//
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// Purpose: User-Mode Control and Status Registers for User Mode Exceptions
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// See RISC-V Privileged Mode Specification 20190608 Table 2.2
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module csrn #(parameter
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USTATUS =12'h000,
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UIE = 12'h004,
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UTVEC = 12'h005,
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USCRATCH = 12'h040,
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UEPC = 12'h041,
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UCAUSE = 12'h042,
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UTVAL = 12'h043,
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UIP = 12'h044) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic CSRNWriteM, UTrapM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
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input logic [`XLEN-1:0] CSRWriteValM,
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output logic [`XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW,
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input logic [11:0] UIP_REGW, UIE_REGW,
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output logic WriteUSTATUSM,
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output logic IllegalCSRNAccessM
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);
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// User mode CSRs below only needed when user mode traps are supported
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if (`N_SUPPORTED) begin:nmode // depricated; consider removing***
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logic WriteUTVECM;
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logic WriteUSCRATCHM, WriteUEPCM;
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logic WriteUCAUSEM, WriteUTVALM;
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logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW;
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logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
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// Write enables
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assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & InstrValidNotFlushedM;
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assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & InstrValidNotFlushedM;
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assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & InstrValidNotFlushedM;
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assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & InstrValidNotFlushedM;
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assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & InstrValidNotFlushedM;
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// CSRs
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flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW);
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flopenr #(`XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW);
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flopenr #(`XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW);
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flopenr #(`XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW);
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flopenr #(`XLEN) UTVALreg(clk, reset, WriteUTVALM, NextMtvalM, UTVAL_REGW);
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// CSR Reads
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always_comb begin
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IllegalCSRNAccessM = 0;
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case (CSRAdrM)
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USTATUS: CSRNReadValM = USTATUS_REGW;
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UTVEC: CSRNReadValM = UTVEC_REGW;
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UIP: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIP_REGW};
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UIE: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIE_REGW};
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USCRATCH: CSRNReadValM = USCRATCH_REGW;
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UEPC: CSRNReadValM = UEPC_REGW;
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UCAUSE: CSRNReadValM = UCAUSE_REGW;
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UTVAL: CSRNReadValM = UTVAL_REGW;
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default: begin
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CSRNReadValM = 0;
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IllegalCSRNAccessM = 1;
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end
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endcase
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end
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end else begin // if not supported
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assign WriteUSTATUSM = 0;
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assign CSRNReadValM = 0;
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assign UEPC_REGW = 0;
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assign UTVEC_REGW = 0;
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assign IllegalCSRNAccessM = 1;
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end
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endmodule
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