cvw/fpga/generator
2023-02-22 15:13:16 -06:00
..
debug
bootrom.txt
insert_debug_comment.sh Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Makefile Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
wally.tcl Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
wave_config.wcfg
xlnx_ahblite_axi_bridge.tcl
xlnx_axi_clock_converter.tcl
xlnx_axi_crossbar.tcl AXI Crossbar is working. Fixed address width in generator script. 2023-02-22 15:13:16 -06:00
xlnx_axi_dwidth_conv_32to64.tcl Connected the axi_sdc_controller with an axi crossbar. 2023-01-13 13:56:01 -06:00
xlnx_axi_dwidth_conv_64to32.tcl Connected the axi_sdc_controller with an axi crossbar. 2023-01-13 13:56:01 -06:00
xlnx_axi_dwidth_converter.tcl Connected the axi_sdc_controller with an axi crossbar. 2023-01-13 13:56:01 -06:00
xlnx_axi_prtcl_conv.tcl Modified makefile. Added axi protocol converter IP. 2023-01-23 19:30:29 -06:00
xlnx_ddr4-vcu108.tcl
xlnx_ddr4-vcu118.tcl
xlnx_ddr4.tcl
xlnx_proc_sys_reset.tcl