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https://github.com/openhwgroup/cvw
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3b07584403
Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.
67 lines
3.0 KiB
Systemverilog
67 lines
3.0 KiB
Systemverilog
///////////////////////////////////////////
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// subwordwrite.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Masking and muxing for subword writes
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module subwordwrite (
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input logic [2:0] LSUPAdrM,
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input logic [2:0] LSUFunct3M,
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input logic [`LLEN-1:0] IMAFWriteDataM,
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output logic [`LLEN-1:0] LittleEndianWriteDataM);
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// Replicate data for subword writes
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if (`LLEN == 128) begin:sww
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always_comb
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case(LSUFunct3M[2:0])
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2'b000: LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
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2'b001: LittleEndianWriteDataM = {8{IMAFWriteDataM[15:0]}}; // sh
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2'b010: LittleEndianWriteDataM = {4{IMAFWriteDataM[31:0]}}; // sw
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2'b011: LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
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default: LittleEndianWriteDataM = IMAFWriteDataM; // sq
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endcase
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end else if (`LLEN == 64) begin:sww
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always_comb
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case(LSUFunct3M[1:0])
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2'b00: LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}}; // sb
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2'b01: LittleEndianWriteDataM = {4{IMAFWriteDataM[15:0]}}; // sh
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2'b10: LittleEndianWriteDataM = {2{IMAFWriteDataM[31:0]}}; // sw
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2'b11: LittleEndianWriteDataM = IMAFWriteDataM; // sd
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endcase
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end else begin:sww // 32-bit
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always_comb
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case(LSUFunct3M[1:0])
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2'b00: LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}}; // sb
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2'b01: LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh
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2'b10: LittleEndianWriteDataM = IMAFWriteDataM; // sw
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default: LittleEndianWriteDataM = IMAFWriteDataM; // shouldn't happen
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endcase
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end
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endmodule
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