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93 lines
3.6 KiB
Systemverilog
93 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// muldiv.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: M extension multiply and divide
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module muldiv (
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input logic clk, reset,
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// Execute Stage interface
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// input logic [`XLEN-1:0] SrcAE, SrcBE,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E, Funct3M,
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input logic MDUE, W64E,
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// Writeback stage
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output logic [`XLEN-1:0] MDUResultW,
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// Divide Done
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output logic DivBusyE,
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// hazards
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input logic StallM, StallW, FlushM, FlushW, TrapM
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);
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logic [`XLEN-1:0] MDUResultM;
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logic [`XLEN-1:0] PrelimResultM;
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logic [`XLEN-1:0] QuotM, RemM;
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logic [`XLEN*2-1:0] ProdM;
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logic DivSignedE;
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logic DivE;
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logic W64M;
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// Multiplier
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mul mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
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// Divide
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// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
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assign DivE = MDUE & Funct3E[2];
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assign DivSignedE = ~Funct3E[0];
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intdivrestoring div(.clk, .reset, .StallM, .TrapM, .DivSignedE, .W64E, .DivE,
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.ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
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// Result multiplexer
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always_comb
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case (Funct3M)
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3'b000: PrelimResultM = ProdM[`XLEN-1:0];
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3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
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3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
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3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
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3'b100: PrelimResultM = QuotM;
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3'b101: PrelimResultM = QuotM;
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3'b110: PrelimResultM = RemM;
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3'b111: PrelimResultM = RemM;
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endcase
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// Handle sign extension for W-type instructions
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flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
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if (`XLEN == 64) begin:resmux // RV64 has W-type instructions
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assign MDUResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
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end else begin:resmux // RV32 has no W-type instructions
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assign MDUResultM = PrelimResultM;
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end
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// Writeback stage pipeline register
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flopenrc #(`XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);
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endmodule // muldiv
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