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https://github.com/openhwgroup/cvw
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366a96a0fc
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU. I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss. This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
124 lines
7.1 KiB
Systemverilog
124 lines
7.1 KiB
Systemverilog
///////////////////////////////////////////
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// ahbcacheinterface.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: August 29, 2022
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// Modified: 18 January 2023
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//
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// Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
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//
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// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahbcacheinterface #(
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parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
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parameter AHBWLOGBWPL, // Log2 of ^
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parameter LINELEN, // Number of bits in cacheline
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parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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parameter READ_ONLY_CACHE
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)(
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input logic HCLK, HRESETn,
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// bus interface controls
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input logic HREADY, // AHB peripheral ready
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output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITE, // AHB 0: Read operation 1: Write operation
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output logic [2:0] HSIZE, // AHB transaction width
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output logic [2:0] HBURST, // AHB burst length
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// bus interface buses
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input logic [`AHBW-1:0] HRDATA, // AHB read data
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output logic [`PA_BITS-1:0] HADDR, // AHB address
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output logic [`AHBW-1:0] HWDATA, // AHB write data
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output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
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input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback
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input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
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input logic Cacheable, // Memory operation is cachable
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
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output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus
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output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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// uncached interface
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input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
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input logic [`LLEN-1:0] WriteDataM, // IEU write data for uncached store
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input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
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input logic [2:0] Funct3, // Size of uncached memory operation
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// lsu/ifu interface
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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output logic BusStall, // Bus is busy with an in flight memory operation
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output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
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localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
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logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
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logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
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logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
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logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
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logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
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genvar index;
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// fetch buffer is made of BEATSPERLINE flip-flops
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for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
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logic [BEATSPERLINE-1:0] CaptureBeat;
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assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
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flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW]));
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end
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mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
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assign HADDR = ({{`PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR;
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mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
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logic [`AHBW-1:0] CacheReadDataWordAHB;
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if(LLENPOVERAHBW > 1) begin
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logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
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genvar index;
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for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
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assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
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end
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assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
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end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
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mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
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// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
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// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
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swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
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flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
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buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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endmodule
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