mirror of
https://github.com/openhwgroup/cvw
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95 lines
2.1 KiB
Verilog
Executable File
95 lines
2.1 KiB
Verilog
Executable File
// testbench
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module tb ();
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reg [63:0] op1;
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reg [63:0] op2;
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reg [2:0] rm;
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reg [3:0] op_type;
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reg P;
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reg OvEn;
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reg UnEn;
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wire [63:0] result;
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wire [4:0] Flags;
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wire Denorm;
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reg clk, tb_clk;
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reg [63:0] yexpected, yexpected_next;
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reg reset;
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reg [63:0] vectornum, errors; // bookkeeping variables
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reg [199:0] testvectors[49999:0]; // array of testvectors
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reg [7:0] flags_expected, flags_expected_next;
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integer handle3;
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integer desc3;
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// instantiate device under test
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fpuadd_testpipe dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, clk);
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always
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begin
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clk = 1;
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tb_clk = 1;
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#5;
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clk = 0;
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#5;
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clk = 1;
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tb_clk = 0;
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#5;
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clk = 0;
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#5;
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end
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initial
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begin
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handle3 = $fopen("../../fpuaddcvt/test_vectors/f64_add_rne.txt");
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$readmemh("../../fpuaddcvt/test_vectors/f64_add_rne.tv", testvectors);
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vectornum = 0; errors = 0;
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reset = 1;#10;reset = 0;
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//reset = 1; #30; reset = 0;
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end
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always @(negedge tb_clk)
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begin
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desc3 = handle3;
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#0 op_type = 4'b0000;
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#0 P = 1'b0;
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#0 rm = 3'b000;
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#0 OvEn = 1'b0;
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#0 UnEn = 1'b0;
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#1; {yexpected_next, flags_expected_next} = {yexpected, flags_expected};
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#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
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#5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags);
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end
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// check results on rising edge of clk - actual results calculated on
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// negedge
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//
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// skip initial cycle
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always @(posedge tb_clk)
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if (~reset)
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begin // skip during reset
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#1;
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if (result !== yexpected) begin
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$display("Error: inputs = %h %h", op1, op2);
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$display(" outputs = %h (%h expected)", result, yexpected);
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errors = errors + 1;
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end
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//else
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//begin
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//$display("Good");
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// end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 200'bx)
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begin
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$display("%d tests completed with %d errors",
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vectornum, errors);
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$stop;
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end
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end // if (~reset)
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endmodule // tb
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