mirror of
https://github.com/openhwgroup/cvw
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74 lines
3.3 KiB
Systemverilog
74 lines
3.3 KiB
Systemverilog
///////////////////////////////////////////
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// wallypipelinedsocwrapper.sv
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//
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// Written: Ross Thompson ross1728@gmail.com 16 June 2023
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// Modified:
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//
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// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,
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// not system verilog.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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//`include "BranchPredictorType.vh"
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`include "config.vh"
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import cvw::*;
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module wallypipelinedsocwrapper (
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input logic clk,
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input logic reset_ext, // external asynchronous reset pin
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output logic reset, // reset synchronized to clk to prevent races on release
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// AHB Interface
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input logic [64-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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output logic HSELEXT,
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// outputs to external memory, shared with uncore memory
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output logic HCLK, HRESETn,
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output logic [55:0] HADDR,
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output logic [64-1:0] HWDATA,
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output logic [64/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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output logic HREADY,
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// I/O Interface
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input logic TIMECLK, // optional for CLINT MTIME counter
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input logic [31:0] GPIOIN, // inputs from GPIO
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output logic [31:0] GPIOOUT, // output values for GPIO
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output logic [31:0] GPIOEN, // output enables for GPIO
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input logic UARTSin, // UART serial data input
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output logic UARTSout, // UART serial data output
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input logic SDCCmdIn, // SDC Command input
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output logic SDCCmdOut, // SDC Command output
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output logic SDCCmdOE, // SDC Command output enable
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input logic [3:0] SDCDatIn, // SDC data input
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output logic SDCCLK // SDC clock
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);
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`include "parameter-defs.vh"
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wallypipelinedsoc #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
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endmodule
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