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https://github.com/openhwgroup/cvw
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97 lines
3.8 KiB
Systemverilog
Executable File
97 lines
3.8 KiB
Systemverilog
Executable File
// Exception logic for the floating point adder. Note: We may
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// actually want to move to where the result is computed.
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module exception_div (Ztype, Invalid, Denorm, ANorm, BNorm, A, B, op_type);
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input [63:0] A; // 1st input operand (op1)
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input [63:0] B; // 2nd input operand (op2)
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input op_type; // Determine operation
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output [2:0] Ztype; // Indicates type of result (Z)
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output Invalid; // Invalid operation exception
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output Denorm; // Denormalized input
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output ANorm; // A is not zero or Denorm
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output BNorm; // B is not zero or Denorm
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wire AzeroM; // '1' if the mantissa of A is zero
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wire BzeroM; // '1' if the mantissa of B is zero
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wire AzeroE; // '1' if the exponent of A is zero
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wire BzeroE; // '1' if the exponent of B is zero
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wire AonesE; // '1' if the exponent of A is all ones
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wire BonesE; // '1' if the exponent of B is all ones
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wire ADenorm; // '1' if A is a denomalized number
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wire BDenorm; // '1' if B is a denomalized number
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wire AInf; // '1' if A is infinite
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wire BInf; // '1' if B is infinite
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wire AZero; // '1' if A is 0
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wire BZero; // '1' if B is 0
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wire ANaN; // '1' if A is a not-a-number
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wire BNaN; // '1' if B is a not-a-number
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wire ASNaN; // '1' if A is a signalling not-a-number
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wire BSNaN; // '1' if B is a signalling not-a-number
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wire ZQNaN; // '1' if result Z is a quiet NaN
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wire ZInf; // '1' if result Z is an infnity
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wire square_root; // '1' if square root operation
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wire Zero; // '1' if result is zero
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parameter [51:0] fifty_two_zeros = 52'h0; // Use parameter?
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// Determine if mantissas are all zeros
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assign AzeroM = (A[51:0] == fifty_two_zeros);
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assign BzeroM = (B[51:0] == fifty_two_zeros);
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// Determine if exponents are all ones or all zeros
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assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52];
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assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52];
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assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]);
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assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]);
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// Determine special cases. Note: Zero is not really a special case.
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assign ADenorm = AzeroE & ~AzeroM;
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assign BDenorm = BzeroE & ~BzeroM;
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assign AInf = AonesE & AzeroM;
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assign BInf = BonesE & BzeroM;
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assign ANaN = AonesE & ~AzeroM;
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assign BNaN = BonesE & ~BzeroM;
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assign ASNaN = ANaN & A[50];
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assign BSNaN = ANaN & A[50];
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assign AZero = AzeroE & AzeroM;
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assign BZero = BzeroE & BzeroE;
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// A and B are normalized if their exponents are not zero.
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assign ANorm = ~AzeroE;
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assign BNorm = ~BzeroE;
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// An "Invalid Operation" exception occurs if (A or B is a signalling NaN)
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// or (A and B are both Infinite)
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assign Invalid = ASNaN | BSNaN | (((AInf & BInf) | (AZero & BZero))&~op_type) |
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(A[63] & op_type);
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// The Denorm flag is set if A is denormlized or if B is normalized
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assign Denorm = ADenorm | BDenorm;
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// The result is a quiet NaN if (an "Invalid Operation" exception occurs)
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// or (A is a NaN) or (B is a NaN).
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assign ZQNaN = Invalid | ANaN | BNaN;
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// The result is zero
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assign Zero = (AZero | BInf)&~op_type | AZero&op_type;
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// The result is +Inf if ((A is Inf) or (B is 0)) and (the
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// result is not a quiet NaN).
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assign ZInf = (AInf | BZero)&~ZQNaN&~op_type | AInf&op_type&~ZQNaN;
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// Set the type of the result as follows:
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// Ztype Result
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// 000 Normal
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// 001 Quiet NaN
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// 010 Infinity
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// 011 Zero
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// 110 DivZero
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assign Ztype[0] = ZQNaN | Zero;
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assign Ztype[1] = ZInf | Zero;
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assign Ztype[2] = BZero&~op_type;
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endmodule // exception
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