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https://github.com/openhwgroup/cvw
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66 lines
3.6 KiB
Systemverilog
66 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// unpack.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: unpack X, Y, Z floating-point inputs
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module unpack import cvw::*; #(parameter cvw_t P) (
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input logic [P.FLEN-1:0] X, Y, Z, // inputs from register file
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input logic [P.FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
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input logic XEn, YEn, ZEn, // input enables
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input logic FPUActive, // Kill inputs when FPU is not active
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
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output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
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output logic XSubnorm, // is X subnormal
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output logic XZero, YZero, ZZero, // is XYZ zero
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax, // does X have the maximum exponent (NaN or Inf)
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output logic [P.FLEN-1:0] XPostBox // X after being properly NaN-boxed
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);
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logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero
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logic XFracZero, YFracZero, ZFracZero; // is the fraction zero
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logic YExpMax, ZExpMax; // is the exponent all 1s
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unpackinput #(P) unpackinputX (.A(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .FPUActive,
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.NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
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.Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero),
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.Subnorm(XSubnorm), .PostBox(XPostBox));
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unpackinput #(P) unpackinputY (.A(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .FPUActive,
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.NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
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.Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero),
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.Subnorm(), .PostBox());
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unpackinput #(P) unpackinputZ (.A(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .FPUActive,
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.NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
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.Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero),
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.Subnorm(), .PostBox());
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endmodule
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