cvw/pipelined/config
2022-07-03 12:26:22 -07:00
..
buildroot Removed references to initialization files 2022-06-23 16:50:27 -07:00
fpga changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
rv32e Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv32gc Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv32i Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv32ic Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv64BP Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv64fp Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
rv64fpquad Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv64gc Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv64i Removed references to initialization files 2022-06-23 16:50:27 -07:00
rv64ic Removed references to initialization files 2022-06-23 16:50:27 -07:00
shared Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work. 2022-06-27 23:55:21 +00:00