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83 lines
3.6 KiB
Systemverilog
83 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// fpuhazard.sv
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//
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// Written: me@KatherineParry.com 19 May 2021
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// Modified:
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//
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// Purpose: Determine forwarding, stalls and flushes for the FPU
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fhazard(
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input logic [4:0] Adr1E, Adr2E, Adr3E, // read data adresses
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input logic FRegWriteM, FRegWriteW, // is the fp register being written to
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input logic [4:0] RdM, RdW, // the adress being written to
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input logic [1:0] FResSelM, // the result being selected
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input logic XEnE, YEnE, ZEnE,
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output logic FStallD, // stall the decode stage
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output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value
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);
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always_comb begin
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// set defaults
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ForwardXE = 2'b00; // choose FRD1E
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ForwardYE = 2'b00; // choose FRD2E
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ForwardZE = 2'b00; // choose FRD3E
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FStallD = 0;
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// if the needed value is in the memory stage - input 1
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if(XEnE)
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if ((Adr1E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W
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// if the needed value is in the memory stage - input 2
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if(YEnE)
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if ((Adr2E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W
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// if the needed value is in the memory stage - input 3
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if(ZEnE)
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if ((Adr3E == RdM) & FRegWriteM)
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// if the result will be FResM (can be taken from the memory stage)
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if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
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else FStallD = 1; // otherwise stall
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// if the needed value is in the writeback stage
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else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W
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end
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endmodule
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