Ross Thompson 44196af61a Have program which checks for sdc init and issues read, but read done is ... not correctly being read back by the software. The error is in how the sdc indicates busy.		2021-09-24 15:53:38 -05:00
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common	setup so the sdc does not need to load a model in the imperas test bench.	2021-09-24 11:30:52 -05:00
imperas-boottim.txt	added sfence to legal instructions, zeroed out rom file to populate for tests	2021-07-23 15:55:08 -04:00
testbench-arch.sv	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
testbench-coremark_bare.sv	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
testbench-coremark.sv	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
testbench-fpga.sv	Have program which checks for sdc init and issues read, but read done is	2021-09-24 15:53:38 -05:00
testbench-imperas.sv	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
testbench-linux.sv	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
testbench-privileged.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00