Ross Thompson 23425c8d71 Write of the SDC address register is correct. The command register is not yet working. ... The root problem is the command register needs to be reset at the end of the SDC transaction.		2021-09-24 18:48:11 -05:00
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crt0	Added special tests for checking the accuracy of global and gshare branch	2021-06-04 11:01:54 -05:00
fpga-blink-led	FPGA test bench and test program.	2021-09-12 20:41:54 -05:00
fpga-test-dram	Have program which checks for sdc init and issues read, but read done is	2021-09-24 15:53:38 -05:00
fpga-test-sdc	Write of the SDC address register is correct. The command register is not yet working.	2021-09-24 18:48:11 -05:00
james_mm	Added special tests for checking the accuracy of global and gshare branch	2021-06-04 11:01:54 -05:00
mibench_qsort	Updated benchmarking code.	2021-05-27 11:48:29 -05:00
sieve	Updated benchmarking code.	2021-05-27 11:48:29 -05:00
simple	Added special tests for checking the accuracy of global and gshare branch	2021-06-04 11:01:54 -05:00
linker1000.x	FPGA test bench and test program.	2021-09-12 20:41:54 -05:00
linker.x	added a whole bunch of interseting test code for branches which does not work.	2021-03-23 13:54:59 -05:00
makefile.inc	Updated branch predictor tests/benchmarks.	2021-05-24 11:13:33 -05:00