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https://github.com/openhwgroup/cvw
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55 lines
2.1 KiB
Systemverilog
55 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// packer.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 5 October 2023
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//
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// Purpose: RISCV kbitmanip pack operation unit
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module packer #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] PackSelect,
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output logic [WIDTH-1:0] PackResult
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);
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logic [WIDTH/2-1:0] lowhalf, highhalf;
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logic [7:0] lowhalfh, highhalfh;
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logic [15:0] lowhalfw, highhalfw;
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logic [WIDTH-1:0] Pack, PackH, PackW;
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assign lowhalf = A[WIDTH/2-1:0];
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assign highhalf = B[WIDTH/2-1:0];
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assign lowhalfh = A[7:0];
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assign highhalfh = B[7:0];
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assign lowhalfw = A[15:0];
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assign highhalfw = B[15:0];
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assign Pack = {highhalf, lowhalf};
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assign PackH = {{(WIDTH-16){1'b0}}, highhalfh, lowhalfh};
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assign PackW = (WIDTH == 64) ? {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw} : Pack; // not implemented for RV32; treat as Pack to simplify logic in result mux
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always_comb
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if (PackSelect[1:0] == 2'b11) PackResult = PackH;
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else if (PackSelect[2] == 1'b0) PackResult = Pack;
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else PackResult = PackW;
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endmodule
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