| .. |
|
old
|
bringing Coremark back to life
|
2021-11-10 12:43:31 -08:00 |
|
slack-notifier
|
added slack notifier for long sims
|
2021-06-22 08:31:41 -04:00 |
|
wave-dos
|
Changes for floating point sims
|
2021-10-27 10:37:35 -07:00 |
|
buildrootBugFinder.py
|
automatic bug finder script
|
2021-11-19 20:25:00 -08:00 |
|
fpga-wave.do
|
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
|
2021-11-17 12:47:19 -06:00 |
|
lint-wally
|
Added synchronizer to reset
|
2021-10-25 10:05:41 -07:00 |
|
linux-wave.do
|
fix recursive signal logging for graphical sims
|
2021-12-08 16:07:26 -08:00 |
|
make-tests.sh
|
add buildroot tv linking to make-tests.sh
|
2021-12-07 11:15:59 -08:00 |
|
Makefile
|
root level makefile added
|
2021-11-17 12:17:56 -08:00 |
|
regression-wally.py
|
increase regression's expectations of buildroot to 246 million
|
2021-12-08 07:01:22 -08:00 |
|
sim-buildroot
|
fix buildroot graphical sim
|
2021-10-31 18:33:43 -07:00 |
|
sim-buildroot-batch
|
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
|
2021-10-25 12:25:32 -07:00 |
|
sim-coremark-batch
|
Added coremark scripts to regression directory
|
2021-12-01 09:08:06 -08:00 |
|
sim-fp64
|
Update to fpdivsqrt to go on posedge as it should. Also an update to
|
2021-10-13 17:14:42 -05:00 |
|
sim-fp64-batch
|
Update to fpdivsqrt to go on posedge as it should. Also an update to
|
2021-10-13 17:14:42 -05:00 |
|
sim-wally
|
Simplified ALU and source multiplexers pass tests
|
2021-12-13 07:57:38 -08:00 |
|
sim-wally-batch
|
Simplified ALU and source multiplexers pass tests
|
2021-12-13 07:57:38 -08:00 |
|
wally-buildroot-batch.do
|
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
|
2021-10-25 12:25:32 -07:00 |
|
wally-buildroot.do
|
fix recursive signal logging for graphical sims
|
2021-12-08 16:07:26 -08:00 |
|
wally-coremark.do
|
Updated coremark testbench with the extra ports from FPGA merge.
|
2021-12-08 13:40:32 -06:00 |
|
wally-fp64-batch.do
|
Update to fpdivsqrt to go on posedge as it should. Also an update to
|
2021-10-13 17:14:42 -05:00 |
|
wally-fp64.do
|
Update to fpdivsqrt to go on posedge as it should. Also an update to
|
2021-10-13 17:14:42 -05:00 |
|
wally-pipelined-batch.do
|
update scripts for handling src/*/* subdirectories
|
2021-10-23 08:54:29 -07:00 |
|
wally-pipelined-fpga.do
|
Merge branch 'main' into fpga
|
2021-11-29 10:06:53 -06:00 |
|
wally-pipelined.do
|
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
|
2021-12-02 18:00:32 -06:00 |
|
wave-all.do
|
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
|
2021-11-17 10:53:17 -08:00 |
|
wave-coremark.do
|
Fixed numerous errors in the preformance counter updates.
|
2021-12-09 11:44:12 -06:00 |
|
wave.do
|
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
|
2021-12-02 18:00:32 -06:00 |
