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https://github.com/openhwgroup/cvw
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52 lines
2.2 KiB
Systemverilog
Executable File
52 lines
2.2 KiB
Systemverilog
Executable File
// This module takes as inputs two operands (op1 and op2)
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// and the result precision (P). Based on the operation and precision,
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// it conditionally converts single precision values to double
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// precision values and modifies the sign of op1.
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// The converted operands are Float1 and Float2.
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module convert_inputs_div (Float1, Float2b, op1, op2, op_type, P);
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input [63:0] op1; // 1st input operand (A)
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input [63:0] op2; // 2nd input operand (B)
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input P; // Result Precision (0 for double, 1 for single)
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input op_type; // Operation
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output [63:0] Float1; // Converted 1st input operand
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output [63:0] Float2b; // Converted 2nd input operand
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wire [63:0] Float2;
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wire Zexp1; // One if the exponent of op1 is zero
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wire Zexp2; // One if the exponent of op2 is zero
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wire Oexp1; // One if the exponent of op1 is all ones
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wire Oexp2; // One if the exponent of op2 is all ones
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// Test if the input exponent is zero, because if it is then the
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// exponent of the converted number should be zero.
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assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] |
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op1[58] | op1[57] | op1[56] | op1[55]);
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assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] |
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op2[58] | op2[57] | op2[56] | op2[55]);
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assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] &
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op1[58] & op1[57] & op1[56] & op1[55]);
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assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] &
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op2[58] & op2[57] & op2[56] &op2[55]);
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// Conditionally convert op1. Lower 29 bits are zero for single precision.
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assign Float1[62:29] = P ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]}
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: op1[62:29];
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assign Float1[28:0] = op1[28:0] & {29{~P}};
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// Conditionally convert op2. Lower 29 bits are zero for single precision.
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assign Float2[62:29] = P ? {op2[62], {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]}
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: op2[62:29];
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assign Float2[28:0] = op2[28:0] & {29{~P}};
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// Set the sign of Float1 based on its original sign
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assign Float1[63] = op1[63];
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assign Float2[63] = op2[63];
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// For sqrt, assign Float2 same as Float1 for simplicity
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assign Float2b = op_type ? Float1 : Float2;
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endmodule // convert_inputs
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