mirror of
https://github.com/openhwgroup/cvw
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b756b248b4
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
607 lines
26 KiB
Systemverilog
607 lines
26 KiB
Systemverilog
///////////////////////////////////////////
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// testbench.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the riscv-arch-test and Imperas suites
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "config.vh"
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`include "tests.vh"
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import cvw::*;
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module testbench;
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/* verilator lint_off WIDTHTRUNC */
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/* verilator lint_off WIDTHEXPAND */
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parameter DEBUG=0;
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parameter TEST="none";
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parameter PrintHPMCounters=1;
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parameter BPRED_LOGGER=0;
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parameter I_CACHE_ADDR_LOGGER=0;
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parameter D_CACHE_ADDR_LOGGER=0;
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`include "parameter-defs.vh"
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logic clk;
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logic reset_ext, reset;
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logic ResetMem;
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// DUT signals
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logic [P.AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [P.PA_BITS-1:0] HADDR;
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logic [P.AHBW-1:0] HWDATA;
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logic [P.XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
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logic UARTSin, UARTSout;
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logic SDCCLK;
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logic SDCCmdIn;
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logic SDCCmdOut;
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logic SDCCmdOE;
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logic [3:0] SDCDatIn;
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tri1 [3:0] SDCDat;
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tri1 SDCCmd;
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logic HREADY;
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logic HSELEXT;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string];
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int test, i, errors, totalerrors;
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string outputfile;
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integer outputFilePointer;
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string tests[];
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logic DCacheFlushDone, DCacheFlushStart;
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logic riscofTest;
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logic Validate;
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logic SelectTest;
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// pick tests based on modes supported
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initial begin
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$display("TEST is %s", TEST);
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//tests = '{};
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if (P.XLEN == 64) begin // RV64
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case (TEST)
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"arch64i": tests = arch64i;
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"arch64priv": tests = arch64priv;
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"arch64c": if (P.C_SUPPORTED)
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if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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else tests = {arch64c};
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"arch64m": if (P.M_SUPPORTED) tests = arch64m;
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"arch64f": if (P.F_SUPPORTED) tests = arch64f;
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"arch64d": if (P.D_SUPPORTED) tests = arch64d;
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"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
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"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
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"arch64zi": if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
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"imperas64i": tests = imperas64i;
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"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
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"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
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"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
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"wally64a": if (P.A_SUPPORTED) tests = wally64a;
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"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
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else tests = imperas64iNOc;
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"custom": tests = custom;
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"wally64i": tests = wally64i;
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"wally64priv": tests = wally64priv;
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"wally64periph": tests = wally64periph;
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"coremark": tests = coremark;
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"fpga": tests = fpga;
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"ahb" : tests = ahb;
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"coverage64gc" : tests = coverage64gc;
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"arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba;
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"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
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"arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc;
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"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
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endcase
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end else begin // RV32
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case (TEST)
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"arch32i": tests = arch32i;
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"arch32priv": tests = arch32priv;
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"arch32c": if (P.C_SUPPORTED)
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if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
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else tests = {arch32c};
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"arch32m": if (P.M_SUPPORTED) tests = arch32m;
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"arch32f": if (P.F_SUPPORTED) tests = arch32f;
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"arch32d": if (P.D_SUPPORTED) tests = arch32d;
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"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
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"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
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"arch32zi": if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
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"imperas32i": tests = imperas32i;
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"imperas32f": if (P.F_SUPPORTED) tests = imperas32f;
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"imperas32m": if (P.M_SUPPORTED) tests = imperas32m;
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"wally32a": if (P.A_SUPPORTED) tests = wally32a;
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"imperas32c": if (P.C_SUPPORTED) tests = imperas32c;
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else tests = imperas32iNOc;
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"wally32i": tests = wally32i;
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"wally32e": tests = wally32e;
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"wally32priv": tests = wally32priv;
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"wally32periph": tests = wally32periph;
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"embench": tests = embench;
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"coremark": tests = coremark;
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"arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba;
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"arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb;
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"arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc;
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"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
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endcase
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end
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if (tests.size() == 0) begin
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$display("TEST %s not supported in this configuration", TEST);
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$stop;
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end
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end // initial begin
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// Model the testbench as an fsm.
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// Do this in parts so it easier to verify
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// part 1: build a version which echos the same behavior as the below code, but does not drive anything
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// part 2: drive some of the controls
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// part 3: drive all logic and remove old inital and always @ negedge clk block
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typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
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STATE_INIT_TEST,
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STATE_RESET_MEMORIES,
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STATE_RESET_MEMORIES2,
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STATE_LOAD_MEMORIES,
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STATE_RESET_TEST,
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STATE_RUN_TEST,
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STATE_CHECK_TEST,
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STATE_CHECK_TEST_WAIT,
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STATE_VALIDATE,
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STATE_INCR_TEST} statetype;
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statetype CurrState, NextState;
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logic TestBenchReset;
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logic [2:0] ResetCount, ResetThreshold;
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logic LoadMem;
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logic ResetCntEn;
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logic ResetCntRst;
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string signame, memfilename, pathname;
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integer begin_signature_addr;
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assign ResetThreshold = 3'd5;
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initial begin
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TestBenchReset = 1;
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# 100;
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TestBenchReset = 0;
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end
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always_ff @(posedge clk)
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if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
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else CurrState <= #1 NextState;
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// fsm next state logic
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always_comb begin
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// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
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// and tests[0] == "2" refers to WallyRiscvArchTests
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riscofTest = tests[0] == "1" | tests[0] == "2";
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pathname = tvpaths[tests[0].atoi()];
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case(CurrState)
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STATE_TESTBENCH_RESET: NextState = STATE_INIT_TEST;
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STATE_INIT_TEST: NextState = STATE_RESET_MEMORIES;
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STATE_RESET_MEMORIES: NextState = STATE_RESET_MEMORIES2;
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STATE_RESET_MEMORIES2: NextState = STATE_LOAD_MEMORIES; // Give the reset enough time to ensure the bus is reset before loading the memories.
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STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST;
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STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
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else NextState = STATE_RUN_TEST;
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STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
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else NextState = STATE_RUN_TEST;
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STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE;
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else NextState = STATE_CHECK_TEST_WAIT;
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STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE;
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else NextState = STATE_CHECK_TEST_WAIT;
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STATE_VALIDATE: NextState = STATE_INIT_TEST;
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STATE_INCR_TEST: NextState = STATE_INIT_TEST;
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default: NextState = STATE_TESTBENCH_RESET;
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endcase
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end // always_comb
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// fsm output control logic
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assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST |
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CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 |
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CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
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// this initialization is very expensive, only do it for coremark.
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assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
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assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
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assign ResetCntRst = CurrState == STATE_INIT_TEST;
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assign ResetCntEn = CurrState == STATE_RESET_TEST;
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assign Validate = CurrState == STATE_VALIDATE;
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assign SelectTest = CurrState == STATE_INIT_TEST;
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// fsm reset counter
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counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
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////////////////////////////////////////////////////////////////////////////////
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// Find the test vector files and populate the PC to function label converter
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////////////////////////////////////////////////////////////////////////////////
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logic [P.XLEN-1:0] testadr;
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assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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always @(posedge clk) begin
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if(SelectTest) begin
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (riscofTest) begin
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ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
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end else begin
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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end
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
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// the addr of each label and fill the array. To expand, add more elements to this array
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// and initialize them to zero (also initilaize them to zero at the start of the next test)
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if(!P.FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Verify the test ran correctly by checking the memory against a known signature.
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////////////////////////////////////////////////////////////////////////////////
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if(TestBenchReset) test = 1;
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if (TEST == "coremark")
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if (dut.core.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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if(Validate) begin
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench
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// python speed script to calculate embench speed score.
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// also, begin_signature contains the results of the self checking mechanism,
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// which will be read by the python script for error checking
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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outputFilePointer = $fopen(outputfile, "w");
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i = 0;
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testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
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while ($unsigned(i) < $unsigned(5'd5)) begin
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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end
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$fclose(outputFilePointer);
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$display("Embench Benchmark: created output file: %s", outputfile);
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end else if (TEST == "coverage64gc") begin
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$display("Coverage tests don't get checked");
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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end
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if (!begin_signature_addr)
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution
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CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
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end
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if(errors > 0) totalerrors = totalerrors + 1;
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test = test + 1; // *** this probably needs to be moved.
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Some memories are not reset, but should be zeros or set to some initial value for simulation
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////////////////////////////////////////////////////////////////////////////////
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integer adrindex;
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if (P.UNCORE_RAM_SUPPORTED) `define TB_UNCORE_RAM_SUPPORTED;
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if (P.BPRED_SUPPORTED) `define TB_BPRED_SUPPORTED;
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if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) `define TB_BHT;
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always @(posedge clk) begin
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if (ResetMem) // program memory is sometimes reset
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if (P.UNCORE_RAM_SUPPORTED) begin
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`ifdef TB_UNCORE_RAM_SUPPORTED
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
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`endif
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end
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if(reset) begin // branch predictor must always be reset
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if (P.BPRED_SUPPORTED) begin
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`ifdef TB_BPRED_SUPPORTED
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// local history only
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if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) begin
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`ifdef TB_BHT
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for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
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dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
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`endif
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end
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// these are both always included if there is a bpred
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for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
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dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
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dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
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`endif
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// load memories with program image
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////////////////////////////////////////////////////////////////////////////////
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if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator
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if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
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if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
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if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
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always @(posedge clk) begin
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if (LoadMem) begin
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if (P.FPGA) begin
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`ifdef TB_FPGA
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string romfilename, sdcfilename;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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// shorten sdc timers for simulation
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dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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`endif
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end
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else if (P.IROM_SUPPORTED) begin
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`ifdef TB_IROM_SUPPORTED
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$readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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`endif
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end
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else if (P.BUS_SUPPORTED) begin
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`ifdef TB_BUS_SUPPORTED
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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`endif
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end
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if (P.DTIM_SUPPORTED) begin
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`ifdef TB_DTIM_SUPPORTED
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$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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`endif
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end
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$display("Read memfile %s", memfilename);
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Actual hardware
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////////////////////////////////////////////////////////////////////////////////
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// instantiate device to be tested
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assign GPIOIN = 0;
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assign UARTSin = 1;
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if(P.EXT_MEM_SUPPORTED) begin
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ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
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ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
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.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
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end else begin
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assign HREADYEXT = 1;
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assign {HRESPEXT, HRDATAEXT} = '0;
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end
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if(P.FPGA) begin : sdcard
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sdModel sdcard
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(.sdClk(SDCCLK),
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.cmd(SDCCmd),
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.dat(SDCDat));
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assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
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assign SDCCmdIn = SDCCmd;
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assign SDCDatIn = SDCDat;
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end else begin
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assign SDCCmd = '0;
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assign SDCDat = '0;
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end
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wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
|
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
|
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
|
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
|
|
|
// generate clock to sequence tests
|
|
always begin
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|
clk = 1; # 5; clk = 0; # 5;
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|
end
|
|
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|
////////////////////////////////////////////////////////////////////////////////
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|
// Support logic
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Track names of instructions
|
|
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
|
logic [31:0] InstrW;
|
|
flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
|
|
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
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|
dut.core.ifu.InstrRawF[31:0],
|
|
dut.core.ifu.InstrD, dut.core.ifu.InstrE,
|
|
dut.core.ifu.InstrM, InstrW,
|
|
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
|
|
|
// watch for problems such as lockup, reading unitialized memory, bad configs
|
|
watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck
|
|
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
|
|
dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName);
|
|
riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
|
|
loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
|
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
|
|
|
|
// track the current function or global label
|
|
if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName
|
|
FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
|
|
.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
|
|
end
|
|
|
|
|
|
// Termination condition
|
|
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
|
|
// or sw gp,-56(t0) for new Imperas tests
|
|
// or sd gp, -56(t0)
|
|
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
|
|
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
|
if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
|
|
else assign ecf = 0;
|
|
assign DCacheFlushStart = ecf &
|
|
(dut.core.ieu.dp.regf.rf[3] == 1 |
|
|
(dut.core.ieu.dp.regf.we3 &
|
|
dut.core.ieu.dp.regf.a3 == 3 &
|
|
dut.core.ieu.dp.regf.wd3 == 1)) |
|
|
((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
|
|
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
|
|
|
|
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
|
|
|
|
task automatic CheckSignature;
|
|
// This task must be declared inside this module as it needs access to parameter P. There is
|
|
// no way to pass P to the task unless we convert it to a module.
|
|
|
|
input string pathname;
|
|
input string TestName;
|
|
input logic riscofTest;
|
|
input integer begin_signature_addr;
|
|
output integer errors;
|
|
|
|
localparam SIGNATURESIZE = 5000000;
|
|
integer i;
|
|
logic [31:0] sig32[0:SIGNATURESIZE];
|
|
logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
|
|
string signame;
|
|
logic [P.XLEN-1:0] testadr, testadrNoBase;
|
|
|
|
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED2
|
|
|
|
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
|
// clear signature to prevent contamination from previous tests
|
|
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
|
sig32[i] = 'bx;
|
|
end
|
|
if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
|
|
else signame = {pathname, TestName, ".signature.output"};
|
|
// read signature, reformat in 64 bits if necessary
|
|
$readmemh(signame, sig32);
|
|
i = 0;
|
|
while (i < SIGNATURESIZE) begin
|
|
if (P.XLEN == 32) begin
|
|
signature[i] = sig32[i];
|
|
i = i+1;
|
|
end else begin
|
|
signature[i/2] = {sig32[i+1], sig32[i]};
|
|
i = i + 2;
|
|
end
|
|
if (i >= 4 & sig32[i-4] === 'bx) begin
|
|
if (i == 4) begin
|
|
i = SIGNATURESIZE+1; // flag empty file
|
|
$display(" Error: empty test file");
|
|
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
|
end
|
|
end
|
|
|
|
// Check errors
|
|
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
|
i = 0;
|
|
testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
|
|
testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
|
|
/* verilator lint_off INFINITELOOP */
|
|
while (signature[i] !== 'bx) begin
|
|
logic [P.XLEN-1:0] sig;
|
|
if (P.DTIM_SUPPORTED) begin
|
|
`ifdef TB_DTIM_SUPPORTED2
|
|
//sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
|
|
`endif
|
|
end
|
|
else if (P.UNCORE_RAM_SUPPORTED) begin
|
|
`ifdef TB_UNCORE_RAM_SUPPORTED
|
|
sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
|
|
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
|
|
`endif
|
|
end
|
|
if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
|
errors = errors+1;
|
|
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
|
|
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
|
|
$stop; //***debug
|
|
end
|
|
i = i + 1;
|
|
end
|
|
/* verilator lint_on INFINITELOOP */
|
|
if (errors == 0) begin
|
|
$display("%s succeeded. Brilliant!!!", TestName);
|
|
end else begin
|
|
$display("%s failed with %d errors. :(", TestName, errors);
|
|
//totalerrors = totalerrors+1;
|
|
end
|
|
|
|
endtask //
|
|
|
|
/* verilator lint_on WIDTHTRUNC */
|
|
/* verilator lint_on WIDTHEXPAND */
|
|
|
|
endmodule
|
|
|
|
/* verilator lint_on STMTDLY */
|
|
/* verilator lint_on WIDTH */
|
|
|
|
task automatic updateProgramAddrLabelArray;
|
|
/* verilator lint_off WIDTHTRUNC */
|
|
/* verilator lint_off WIDTHEXPAND */
|
|
input string ProgramAddrMapFile, ProgramLabelMapFile;
|
|
inout integer ProgramAddrLabelArray [string];
|
|
// Gets the memory location of begin_signature
|
|
integer ProgramLabelMapFP, ProgramAddrMapFP;
|
|
ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
|
|
ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
|
|
|
|
|
|
if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
|
|
// *** RT: I'm a bit confused by the required initialization here.
|
|
ProgramAddrLabelArray["begin_signature"] = 0;
|
|
ProgramAddrLabelArray["tohost"] = 0;
|
|
while (!$feof(ProgramLabelMapFP)) begin
|
|
string label, adrstr;
|
|
integer returncode;
|
|
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
|
|
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
|
|
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
|
|
end
|
|
end
|
|
$fclose(ProgramLabelMapFP);
|
|
$fclose(ProgramAddrMapFP);
|
|
/* verilator lint_on WIDTHTRUNC */
|
|
/* verilator lint_on WIDTHEXPAND */
|
|
endtask
|
|
|