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https://github.com/openhwgroup/cvw
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6ccbdc372d
Possible change to walker, dcache, tlb addressing. Improves the naming of address signals. But has a problem when the walker finishes the dcache does not get the correct address on the cycle the DTLB is updated. This leads to incorrect index selection in the dcache.
69 lines
3.5 KiB
Systemverilog
69 lines
3.5 KiB
Systemverilog
///////////////////////////////////////////
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// tlbmixer.sv
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//
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// Written: David Harris and kmacsaigoren@hmc.edu 7 June 2021
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// Modified:
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//
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//
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// Purpose: Takes two page numbers and replaces segments of the first page
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// number with segments from the second, based on the page type.
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// NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module tlbmixer (
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input logic [`VPN_BITS-1:0] VPN,
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input logic [`PPN_BITS-1:0] PPN,
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input logic [1:0] HitPageType,
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input logic [11:0] Offset,
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input logic TLBHit,
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output logic [`PA_BITS-1:0] TLBPAdr
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);
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localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS;
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logic [`PPN_BITS-1:0] ZeroExtendedVPN;
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logic [`PPN_BITS-1:0] PageNumberMask;
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logic [`PPN_BITS-1:0] PPNMixed;
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// produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages
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generate
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if (`XLEN == 32)
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// kilopage: 22 bits of PPN, 0 bits of VPN
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// megapage: 12 bits of PPN, 10 bits of VPN
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mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask);
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else
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// kilopage: 44 bits of PPN, 0 bits of VPN
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// megapage: 35 bits of PPN, 9 bits of VPN
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// gigapage: 26 bits of PPN, 18 bits of VPN
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// terapage: 17 bits of PPN, 27 bits of VPN
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mux4 #(44) pnm(44'h00000000000, 44'h000000001FF, 44'h0000003FFFF, 44'h00007FFFFFF, HitPageType, PageNumberMask);
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endgenerate
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// merge low segments of VPN with high segments of PPN decided by the pagetype.
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assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
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assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; //
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//mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed);
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//assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
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// Output the hit physical address if translation is currently on.
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// Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
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mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
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endmodule
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