mirror of
https://github.com/openhwgroup/cvw
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111 lines
4.7 KiB
Systemverilog
111 lines
4.7 KiB
Systemverilog
///////////////////////////////////////////
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// ahbapbbridge.sv
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//
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// Written: David_Harris@hmc.edu & Nic Lucio 7 June 2022
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//
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// Purpose: AHB to APB bridge
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahbapbbridge #(PERIPHS = 2) (
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input logic HCLK, HRESETn,
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input logic [PERIPHS-1:0] HSEL,
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input logic [`PA_BITS-1:0] HADDR,
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input logic [`XLEN-1:0] HWDATA,
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input logic [`XLEN/8-1:0] HWSTRB,
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input logic HWRITE,
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input logic [1:0] HTRANS,
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input logic HREADY,
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// input logic [3:0] HPROT, // not used
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output logic [`XLEN-1:0] HRDATA,
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output logic HRESP, HREADYOUT,
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output logic PCLK, PRESETn,
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output logic [PERIPHS-1:0] PSEL,
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output logic PWRITE,
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output logic PENABLE,
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output logic [31:0] PADDR,
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output logic [`XLEN-1:0] PWDATA,
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// output logic [2:0] PPROT, // not used
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output logic [`XLEN/8-1:0] PSTRB,
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// output logic PWAKEUP // not used
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input logic [PERIPHS-1:0] PREADY,
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input var [PERIPHS-1:0][`XLEN-1:0] PRDATA
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);
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logic initTrans, initTransSel, initTransSelD;
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logic nextPENABLE;
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logic PREADYOUT;
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// convert AHB to APB signals
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assign PCLK = HCLK;
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assign PRESETn = HRESETn;
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// identify start of a transaction
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assign initTrans = HTRANS[1] & HREADY; // start a transaction when the bus is ready and an active transaction is requested
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assign initTransSel = initTrans & |HSEL; // capture data and address if any of the peripherals are selected
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// delay AHB Address phase signals to align with AHB Data phase because APB expects them at the same time
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flopen #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
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flopenr #(1) writereg(HCLK, ~HRESETn, HREADY, HWRITE, PWRITE);
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flopenr #(PERIPHS) selreg(HCLK, ~HRESETn, HREADY, HSEL & {PERIPHS{initTrans}}, PSEL);
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// PPROT[2:0] = {Data/InstrB, Secure, Privileged};
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// assign PPROT = {~HPROT[0], 1'b0, HPROT[1]}; // protection not presently used
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// assign PWAKEUP = 1'b1; // not used
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// AHB Data phase signal doesn't need delay. Note that they are guaranteed to remain stable until READY is asserted
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assign PWDATA = HWDATA;
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assign PSTRB = HWSTRB;
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// enable logic: goes high a cycle after initTrans, then back low on cycle after desired PREADY is asserted
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// cycle1: AHB puts HADDR, HWRITE, HSEL on bus. initTrans is 1, and these are captured
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// cycle2: AHB puts HWDATA on the bus. This effectively extends the setup phase
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// cycle3: bridge raises PENABLE. Peripheral typically responds with PREADY.
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// Read occurs by end of cycle. Write occurs at end of cycle.
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flopr #(1) inittransreg(HCLK, ~HRESETn, initTransSel, initTransSelD);
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assign nextPENABLE = PENABLE ? ~HREADY : initTransSelD;
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flopr #(1) enablereg(HCLK, ~HRESETn, nextPENABLE, PENABLE);
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// result and ready multiplexer
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int i;
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always_comb begin
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// default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
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// *** also could assert ready right away
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HRDATA = 0;
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PREADYOUT = 1'b1;
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for (i=0; i<PERIPHS; i++) begin
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if (PSEL[i]) begin // highest numbered peripheral has priority, but multiple PSEL should never be asserted
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HRDATA = PRDATA[i];
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PREADYOUT = PREADY[i];
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end
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end
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end
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assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before access phase
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// resp logic
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assign HRESP = 0; // bridge never indicates errors
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endmodule
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