mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
40bdcda32d
There were two major bugs with the predictor. First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome). Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted. This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
116 lines
4.0 KiB
Systemverilog
116 lines
4.0 KiB
Systemverilog
//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified: Brett Mathis
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// RV32 or RV64: XLEN = 32 or 64
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`define BUILDROOT 0
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`define BUSYBEAR 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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//`define MISA (32'h00000105)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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`define ZCSR_SUPPORTED 1
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`define COUNTERS 31
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`define ZCOUNTERS_SUPPORTED 1
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
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`define N_SUPPORTED 0
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`define M_MODE (2'b11)
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`define S_MODE (2'b01)
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`define U_MODE (2'b00)
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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// Address space
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`define RESET_VECTOR 64'h0000000000000000
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// Bus Interface width
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`define AHBW 64
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00800000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h00000000
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`define TIMRANGE 32'h07FFFFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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`define GPIORANGE 32'h000000FF
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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`define PLICBASE 32'h0C000000
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`define PLICRANGE 32'h03FFFFFF
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Busybear special CSR config to match OVPSim
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`define OVPSIM_CSR_CONFIG 0
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 4
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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//`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define BPTYPE "BPGLOBAL" // BPTWOBIT or "BPGSHARE" or BPLOCALPAg or BPGSHARE
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`define TESTSBP 1
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