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https://github.com/openhwgroup/cvw
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84 lines
2.6 KiB
Systemverilog
84 lines
2.6 KiB
Systemverilog
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///////////////////////////////////////////
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// cnt.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu>
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// Created: 4 February 2023
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// Modified:
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//
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// Purpose: Count Instruction Submodule
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//
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// Documentation: RISC-V System on Chip Design Chapter ***
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cnt #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic W64, // Indicates word operation
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output logic [WIDTH-1:0] czResult, // count zeros result
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output logic [WIDTH-1:0] cpopResult);// population count result
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//count instructions
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logic [WIDTH-1:0] lzcA, popcntA;
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logic [WIDTH-1:0] revA;
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//in both rv64, rv32
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bitreverse #(WIDTH) brtz(.a(A), .b(revA));
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//only in rv64
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if (WIDTH==64) begin
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//NOTE: signal widths can be decreased
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always_comb begin
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//clz input select mux
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case({B[4:0],W64})
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6'b00000_0: lzcA = A; //clz
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6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw
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6'b00001_0: lzcA = revA; //ctz
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6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw
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default: lzcA = A;
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endcase
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//cpop select mux
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case ({B[4:0],W64})
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6'b00010_0: popcntA = A;
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6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]};
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default: popcntA = A;
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endcase
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end
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end
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else begin
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//rv32
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assign popcntA = A;
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always_comb begin
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//clz input slect mux
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case(B[4:0])
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5'b00000: lzcA = A;
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5'b00001: lzcA = revA;
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default: lzcA = A;
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endcase
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end
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end
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//NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later.
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lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult));
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popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult));
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endmodule |