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104 lines
3.5 KiB
Systemverilog
104 lines
3.5 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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// Block Name: fmac.v
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// Author: David Harris
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// Date: 11/2/1995
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//
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// Block Description:
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// This is the top level block of a floating-point multiply/accumulate
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// unit(FMAC). It instantiates the following sub-blocks:
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//
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// array Booth encoding, partial product generation, product summation
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// expgen Exponent summation, compare, and adjust
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// align Alignment shifter
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// add Carry-save adder for accumulate, carry propagate adder
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// lza Leading zero anticipator to control normalization shifter
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// normalize Normalization shifter
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// round Rounding of result
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// exception Handles exceptional cases
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// bypass Handles bypass of result to ReadData1E or ReadData3E inputs
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// sign One bit sign handling block
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// special Catch special cases (inputs = 0 / infinity / etc.)
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//
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// The FMAC computes FmaResultM=ReadData1E*ReadData2E+ReadData3E, rounded with the mode specified by
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// RN, RZ, RM, or RP. The result is optionally bypassed back to
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// the ReadData1E or ReadData3E inputs for use on the next cycle. In addition, four signals
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// are produced: trap, overflow, underflow, and inexact. Trap indicates
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// an infinity, NaN, or denormalized number to be handled in software;
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// the other three signals are IEEE flags.
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//
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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module fma1(ReadData1E, ReadData2E, ReadData3E, FrmE,
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rE, sE, tE, bsE, killprodE, sumshiftE, sumshiftzeroE, aligncntE, aeE
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, xzeroE, yzeroE, zzeroE, xnanE,ynanE, znanE, xdenormE, ydenormE, zdenormE,
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xinfE, yinfE, zinfE, nanE, prodinfE);
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/////////////////////////////////////////////////////////////////////////////
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input logic [63:0] ReadData1E; // input 1
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input logic [63:0] ReadData2E; // input 2
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input logic [63:0] ReadData3E; // input 3
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input logic [2:0] FrmE; // Rounding mode
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output logic [12:0] aligncntE; // status flags
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output logic [105:0] rE; // one result of partial product sum
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output logic [105:0] sE; // other result of partial products
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output logic [163:0] tE; // output logic of alignment shifter
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output logic [12:0] aeE; // multiplier expoent
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output logic bsE; // sticky bit of addend
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output logic killprodE; // ReadData3E >> product
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output logic xzeroE;
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output logic yzeroE;
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output logic zzeroE;
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output logic xdenormE;
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output logic ydenormE;
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output logic zdenormE;
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output logic xinfE;
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output logic yinfE;
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output logic zinfE;
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output logic xnanE;
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output logic ynanE;
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output logic znanE;
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output logic nanE;
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output logic prodinfE;
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output logic [8:0] sumshiftE;
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output logic sumshiftzeroE;
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// Internal nodes
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// output logic [12:0] aligncntE; // shift count for alignment
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logic prodof; // ReadData1E*ReadData2E out of range
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// Instantiate fraction datapath
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multiply multiply(.xman(ReadData1E[51:0]), .yman(ReadData2E[51:0]), .*);
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align align(.zman(ReadData3E[51:0]),.*);
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// Instantiate exponent datapath
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expgen1 expgen1(.xexp(ReadData1E[62:52]),.yexp(ReadData2E[62:52]),.zexp(ReadData3E[62:52]),.*);
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// Instantiate special case detection across datapath & exponent path
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special special(.*);
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// Instantiate control output logic
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flag1 flag1(.*);
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endmodule
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