mirror of
https://github.com/openhwgroup/cvw
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70 lines
1.5 KiB
Systemverilog
70 lines
1.5 KiB
Systemverilog
module ha (C, S, A, B) ;
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input A, B;
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output S, C;
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assign S = A^B;
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assign C = A&B;
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endmodule // HA
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// module fa (input logic a, b, c, output logic sum, carry);
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// assign sum = a^b^c;
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// assign carry = a&b|a&c|b&c;
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// endmodule // fa
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// module csa #(parameter WIDTH=8) (a, b,c, sum, carry, cout);
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// input logic [WIDTH-1:0] a, b, c;
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// output logic [WIDTH-1:0] sum, carry;
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// output logic cout;
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// logic [WIDTH:0] carry_temp;
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// genvar i;
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// generate
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// for (i=0;i<WIDTH;i=i+1)
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// begin : genbit
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// fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
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// end
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// endgenerate
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// assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0};
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// assign cout = carry_temp[WIDTH];
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// endmodule // csa
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module FA_array (S, C, A, B, Ci) ;
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parameter n = 32;
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input [n-1:0] A;
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input [n-1:0] B;
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input [n-1:0] Ci;
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output [n-1:0] S;
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output [n-1:0] C;
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wire [n-1:0] n0;
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wire [n-1:0] n1;
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wire [n-1:0] n2;
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genvar i;
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generate
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for (i = 0; i < n; i = i + 1) begin : index
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fa FA1(.sum(S[i]), .carry(C[i]), .a(A[i]), .b(B[i]), .c(Ci[i]));
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end
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endgenerate
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endmodule // FA_array
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module HA_array (S, C, A, B) ;
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parameter n = 32;
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input [n-1:0] A, B;
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output [n-1:0] S, C;
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genvar i;
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generate
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for (i = 0; i < n; i = i + 1) begin : index
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ha ha1(.S(S[i]), .C(C[i]), .A(A[i]), .B(B[i]));
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end
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endgenerate
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endmodule // HA_array
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