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https://github.com/openhwgroup/cvw
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93 lines
4.1 KiB
Systemverilog
93 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// wally-pipelinedsoc.sv
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//
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// Written: David_Harris@hmc.edu 6 November 2020
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// Modified:
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//
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// Purpose: System on chip including pipelined processor and uncore memories/peripherals
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//
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// Documentation: RISC-V System on Chip Design (Figure 6.20)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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import cvw::*; // global CORE-V-Wally parameters
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module wallypipelinedsoc (
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input logic clk,
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input logic reset_ext, // external asynchronous reset pin
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output logic reset, // reset synchronized to clk to prevent races on release
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// AHB Interface
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input logic [AHBW-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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output logic HSELEXT,
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// outputs to external memory, shared with uncore memory
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output logic HCLK, HRESETn,
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output logic [PA_BITS-1:0] HADDR,
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output logic [AHBW-1:0] HWDATA,
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output logic [XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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output logic HREADY,
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// I/O Interface
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input logic TIMECLK, // optional for CLINT MTIME counter
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input logic [31:0] GPIOPinsIn, // inputs from GPIO
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output logic [31:0] GPIOPinsOut, // output values for GPIO
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output logic [31:0] GPIOPinsEn, // output enables for GPIO
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input logic UARTSin, // UART serial data input
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output logic UARTSout, // UART serial data output
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input logic SDCCmdIn, // SDC Command input
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output logic SDCCmdOut, // SDC Command output
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output logic SDCCmdOE, // SDC Command output enable
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input logic [3:0] SDCDatIn, // SDC data input
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output logic SDCCLK // SDC clock
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);
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// Uncore signals
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logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
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logic HRESP; // response from AHB
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logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
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logic [63:0] MTIME_CLINT; // from CLINT to CSRs
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logic MExtInt,SExtInt; // from PLIC
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// synchronize reset to SOC clock domain
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synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
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// instantiate processor and internal memories
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wallypipelinedcore core(.clk, .reset,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
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.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
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.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
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);
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// instantiate uncore if a bus interface exists
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if (BUS_SUPPORTED) begin : uncore
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uncore uncore(.HCLK, .HRESETn, .TIMECLK,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
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.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
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.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin,
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.UARTSout, .MTIME_CLINT,
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.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
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end
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endmodule
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