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59 lines
3.0 KiB
Systemverilog
59 lines
3.0 KiB
Systemverilog
///////////////////////////////////////////
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// redundantmul.sv
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//
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// Written: David_Harris@hmc.edu and ssanghai@hm.edu 10/11/2021
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// Modified:
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//
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// Purpose: multiplier with output in redundant carry-sum form
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// This can be faster than a mutiplier that requires a final adder to obtain the nonredundant answer.
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// The module has several implementations controlled by the DESIGN_COMPILER flag.
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// When DESIGN_COMPILER = 1, use the Synopsys DesignWare DW02_multp block. This will give highest quality results
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// but doesn't work in simulation or when using different tools
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// When DESIGN_COMPILER = 2, use the Wally mult_cs block with Radix 2 Booth encoding and a Wallace Tree
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// This simulates and synthesizes, but quality of results ae lower than DesignWare
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// Otherwise, just use a nonredundant multiplier and set one word to 0. This is best for FPGAs, which have
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// block multipliers, and also simulates fastest.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module redundantmul #(parameter WIDTH =8)(
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input logic [WIDTH-1:0] a,b,
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output logic [2*WIDTH-1:0] out0, out1);
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if (`DESIGN_COMPILER == 1) begin:mul
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logic [2*WIDTH-1+2:0] tmp_out0;
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logic [2*WIDTH-1+2:0] tmp_out1;
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DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
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assign out0 = tmp_out0[2*WIDTH-1:0];
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assign out1 = tmp_out1[2*WIDTH-1:0];
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end else begin:mul // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs.
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assign out0 = a * b;
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assign out1 = 0;
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end
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endmodule
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