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https://github.com/openhwgroup/cvw
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17 lines
422 B
Systemverilog
17 lines
422 B
Systemverilog
module sync_w2r #(parameter ADDRSIZE = 4)
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(rq2_wptr, wptr, rclk, rrst_n);
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input logic [ADDRSIZE:0] wptr;
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input logic rclk;
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input logic rrst_n;
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output logic [ADDRSIZE:0] rq2_wptr;
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logic [ADDRSIZE:0] rq1_wptr;
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always @(posedge rclk or negedge rrst_n)
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if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
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else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
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endmodule // sync_w2r
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