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25 lines
707 B
Systemverilog
25 lines
707 B
Systemverilog
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// DATASIZE = Memory data word width
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// ADDRSIZE = Number of mem address bits
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module fifomem #(parameter DATASIZE = 8,
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parameter ADDRSIZE = 4)
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(rdata, wdata, waddr, raddr, wclken, wfull, wclk);
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input logic [DATASIZE-1:0] wdata;
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input logic [ADDRSIZE-1:0] waddr;
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input logic [ADDRSIZE-1:0] raddr;
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input logic wclken;
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input logic wfull;
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input logic wclk;
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output logic [DATASIZE-1:0] rdata;
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// RTL Verilog memory model
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localparam DEPTH = 1 << ADDRSIZE;
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logic [DATASIZE-1:0] mem [0:DEPTH-1];
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assign rdata = mem[raddr];
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always @(posedge wclk)
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if (wclken && !wfull) mem[waddr] <= wdata;
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endmodule // fifomem
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