mirror of
https://github.com/openhwgroup/cvw
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115 lines
4.6 KiB
Systemverilog
115 lines
4.6 KiB
Systemverilog
///////////////////////////////////////////
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// ahbxuiconverter.sv
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//
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// Written: infinitymdm@gmail.com
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//
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// Purpose: AHB to Xilinx UI converter
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ahbxuiconverter #(parameter ADDR_SIZE = 31,
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parameter DATA_SIZE = 64) (
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// AHB signals
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input logic HCLK,
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input logic HRESETn,
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input logic HSEL,
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input logic [ADDR_SIZE-1:0] HADDR,
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input logic [DATA_SIZE-1:0] HWDATA,
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input logic [DATA_SIZE/8-1:0] HWSTRB,
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input logic HWRITE,
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input logic [1:0] HTRANS,
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input logic HREADY,
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output logic [DATA_SIZE-1:0] HRDATA,
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output logic HRESP,
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output logic HREADYOUT,
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// UI signals
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output logic sys_reset,
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input logic ui_clk, // from PLL
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input logic ui_clk_sync_rst,
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output logic [ADDR_SIZE-1:0] app_addr, // Double check this width
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output logic [2:0] app_cmd,
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output logic app_en,
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input logic app_rdy,
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output logic app_wdf_wren,
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output logic [DATA_SIZE-1:0] app_wdf_data,
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output logic [DATA_SIZE/8-1:0] app_wdf_mask,
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output logic app_wdf_end,
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input logic app_wdf_rdy,
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input logic [DATA_SIZE-1:0] app_rd_data,
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input logic app_rd_data_end,
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input logic app_rd_data_valid,
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input logic init_calib_complete
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);
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assign sys_reset = ~HRESETn;
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// Enable this peripheral when:
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// a) selected, AND
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// b) a transfer is started, AND
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// c) the bus is ready
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logic ahbEnable;
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assign ahbEnable = HSEL & HTRANS[1] & HREADY;
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// UI is ready for a command when initialized and ready to read and write
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logic uiReady;
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assign uiReady = app_rdy & app_wdf_rdy & init_calib_complete;
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// Buffer the input down to ui_clk speed
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logic [ADDR_SIZE-1:0] addr;
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logic [DATA_SIZE-1:0] data;
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logic [DATA_SIZE/8-1:0] mask;
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logic cmdEnable, cmdWrite;
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logic cmdwfull, cmdrempty;
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// FIFO needs addr + (data + mask) + (enable + write)
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fifo #(ADDR_SIZE + 9*DATA_SIZE/8 + 2, 32) cmdfifo (
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.wdata({HADDR, HWDATA, HWSTRB, ahbEnable, HWRITE}),
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.winc(ahbEnable), .wclk(HCLK), .wrst_n(HRESETn),
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.rinc(uiReady), .rclk(ui_clk), .rrst_n(~ui_clk_sync_rst),
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.rdata({addr, data, mask, cmdEnable, cmdWrite}),
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.wfull(cmdwfull), .rempty(cmdrempty)
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);
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// Delay transactions 1 clk so we can set wren on the cycle after write commands
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flopen #(ADDR_SIZE) addrreg (ui_clk, uiReady, addr, app_addr);
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flopenr #(3) cmdreg (ui_clk, ui_clk_sync_rst, uiReady, {2'b0, ~cmdWrite}, app_cmd);
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flopenr #(1) cmdenreg (ui_clk, ui_clk_sync_rst, uiReady, cmdEnable, app_en);
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flopenr #(1) wrenreg (ui_clk, ui_clk_sync_rst, uiReady, ~app_cmd[0], app_wdf_wren);
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flopenr #(DATA_SIZE) datareg (ui_clk, ui_clk_sync_rst, uiReady, data, app_wdf_data);
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flopenr #(DATA_SIZE/8) maskreg (ui_clk, ui_clk_sync_rst, uiReady, mask, app_wdf_mask);
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assign app_wdf_end = app_wdf_wren; // Since AHB will always put data on the bus after a write cmd, this is always valid
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// Return read data at HCLK speed TODO: Double check that rinc is correct
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logic respwfull, resprempty;
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fifo #(DATA_SIZE, 16) respfifo (
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.wdata(app_rd_data),
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.winc(app_rd_data_valid), .wclk(ui_clk), .wrst_n(~ui_clk_sync_rst),
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.rinc(ahbEnable), .rclk(HCLK), .rrst_n(HRESETn),
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.rdata(HRDATA),
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.wfull(respwfull), .rempty(resprempty)
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);
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assign HRESP = 0; // do not indicate errors
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assign HREADYOUT = uiReady & ~cmdwfull; // TODO: Double check
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endmodule
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