David Harris 16c8655161 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2022-12-21 14:12:25 -08:00
..
cache	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
ebu	Rough draft of cache flush fsm enhancement.	2022-12-16 15:28:22 -06:00
fpu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-21 19:35:57 +00:00
generic	Memory cleanup	2022-12-20 11:22:26 -08:00
hazard	Explained hazard causes	2022-12-19 09:41:41 -08:00
ieu	IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI	2022-12-20 15:38:30 -08:00
ifu	The optimzied PC+2/4 logic still hanges on wally32priv.	2022-12-21 09:19:34 -06:00
lsu	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
mmu	Moved CPUBusy out of HPTW.	2022-12-11 15:48:00 -06:00
muldiv	Use FlushE to reset integer divider FSM	2022-12-15 11:00:54 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	comment cleanup	2022-12-21 12:39:09 -08:00
uncore	Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.	2022-12-21 09:00:09 -06:00
wally	Moved privileged pc logic into privileged unit.	2022-12-20 17:55:45 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00