mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-28 23:44:29 +00:00
713 lines
26 KiB
Systemverilog
713 lines
26 KiB
Systemverilog
`include "wally-config.vh"
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module testbench();
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logic clk, reset;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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// instantiate device to be tested
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logic [31:0] CheckInstrD;
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logic [`AHBW-1:0] HRDATA;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic UARTSout;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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// instantiate processor and memories
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wallypipelinedsoc dut(.*);
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/**
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* Walk the page table stored in dtim according to sv39 logic and translate a
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* virtual address to a physical address.
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*
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* See section 4.3.2 of the RISC-V Privileged specification for a full
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* explanation of the below algorithm.
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*/
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function logic [`XLEN-1:0] adrTranslator(
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input logic [`XLEN-1:0] adrIn);
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begin
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logic SvMode, PTE_R, PTE_X;
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logic [`XLEN-1:0] SATP, PTE;
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logic [55:0] BaseAdr, PAdr;
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logic [8:0] VPN [0:2];
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logic [11:0] Offset;
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int i;
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// Grab the SATP register from privileged unit
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SATP = dut.hart.priv.csr.SATP_REGW;
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// Split the virtual address into page number segments and offset
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VPN[2] = adrIn[38:30];
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VPN[1] = adrIn[29:21];
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VPN[0] = adrIn[20:12];
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Offset = adrIn[11:0];
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// We do not support sv48; only sv39
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SvMode = SATP[63];
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// Only perform translation if translation is on and the processor is not
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// in machine mode
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if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin
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BaseAdr = SATP[43:0] << 12;
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for (i = 2; i >= 0; i--) begin
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PAdr = BaseAdr + (VPN[i] << 3);
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// dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
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// by 3 (the PTE size) to get the requested 64-bit PTE.
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PTE = dut.uncore.dtim.RAM[PAdr >> 3];
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PTE_R = PTE[1];
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PTE_X = PTE[3];
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if (PTE_R || PTE_X) begin
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// Leaf page found
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break;
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end else begin
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// Go to next level of table
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BaseAdr = PTE[53:10] << 12;
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end
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end
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// Determine which parts of the PTE page number to use based on the
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// level of the page table we reached.
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if (i == 2) begin
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// Gigapage
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assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset};
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end else if (i == 1) begin
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// Megapage
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assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset};
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end else begin
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// Kilopage
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assign adrTranslator = {8'b0, PTE[53:10], Offset};
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end
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end else begin
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// Direct translation if address translation is not on
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assign adrTranslator = adrIn;
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end
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end
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endfunction
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// initialize test
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// read pc trace file
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integer data_file_PC, scan_file_PC;
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initial begin
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data_file_PC = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
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if (data_file_PC == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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integer data_file_PCW, scan_file_PCW;
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initial begin
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data_file_PCW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
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if (data_file_PCW == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read register trace file
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integer data_file_rf, scan_file_rf;
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initial begin
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data_file_rf = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedRegs.txt"}, "r");
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if (data_file_rf == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read CSR trace file
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integer data_file_csr, scan_file_csr;
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initial begin
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data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs2.txt"}, "r");
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if (data_file_csr == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read memreads trace file
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integer data_file_memR, scan_file_memR;
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initial begin
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data_file_memR = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemRead.txt"}, "r");
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if (data_file_memR == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read memwrite trace file
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integer data_file_memW, scan_file_memW;
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initial begin
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data_file_memW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemWrite.txt"}, "r");
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if (data_file_memW == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// initial loading of memories
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initial begin
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$readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
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$readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
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end
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integer warningCount = 0;
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integer instrs;
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//logic[63:0] adrTranslation[4:0];
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//string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"};
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//initial begin
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// for(int i=0; i<5; i++) begin
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// adrTranslation[i] = 64'b0;
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// end
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//end
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//function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func);
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// if (adr[11:0] !== adrExpected[11:0]) begin
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// equal = 1'b0;
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// end else begin
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// equal = 1'b1;
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// if ((adr+adrTranslation[func]) !== adrExpected) begin
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// adrTranslation[func] = adrExpected - adr;
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// $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs);
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// warningCount += 1;
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// end
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// end
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//endfunction
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// pretty sure this isn't necessary anymore, but keeping this for now since its easier
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function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func);
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equal = adr === adrExpected;
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endfunction
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`define ERROR \
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#10; \
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$display("processed %0d instructions with %0d warnings", instrs, warningCount); \
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$stop;
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logic [63:0] pcExpected;
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logic [63:0] regExpected;
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integer regNumExpected;
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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genvar i;
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generate
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for(i=1; i<32; i++) begin
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always @(dut.hart.ieu.dp.regf.rf[i]) begin
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if ($time == 0) begin
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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end else begin
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scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (i != regNumExpected) begin
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$display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, instrs, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]);
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`ERROR
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end
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if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin
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$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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//if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
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// force dut.hart.ieu.dp.regf.rf[i] = regExpected;
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// release dut.hart.ieu.dp.regf.rf[i];
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//end
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end
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end
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end
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endgenerate
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// RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
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// including subwords. Brief explanation on signals:
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//
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// readMask: bitmask of bits to read / write, left-shifted to align with
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// nearest 64-bit boundary - examples
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// HSIZE = 0 -> readMask = 11111111
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// HSIZE = 1 -> readMask = 1111111111111111
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//
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// In the linux boot, the processor spends the first ~5 instructions in
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// bootram, before jr jumps to main RAM
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logic [63:0] readMask;
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assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
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logic [`XLEN-1:0] readAdrExpected, readAdrTranslated;
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import ahbliteState::*;
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always @(dut.HRDATA) begin
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#2;
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if (dut.hart.MemRWM[1]
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&& (dut.hart.ebu.BusState == MEMREAD || dut.hart.ebu.BusState == ATOMICREAD)
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&& dut.HRDATA !== {64{1'bx}}) begin
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//$display("%0t", $time);
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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`ERROR
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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assign readAdrTranslated = adrTranslator(readAdrExpected);
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if (~equal(HADDR,readAdrTranslated,4)) begin
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$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrTranslated);
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`ERROR
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end
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if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin
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if (HADDR inside `BUSYBEAR_FIX_READ) begin
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//$display("warning %0t ps, instr %0d, adr %0d: forcing HRDATA to expected: %x, %x", $time, instrs, HADDR, HRDATA, dut.HRDATA);
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force dut.uncore.HRDATA = HRDATA;
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#9;
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release dut.uncore.HRDATA;
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warningCount += 1;
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end else begin
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$display("%0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
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`ERROR
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end
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end
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//end else if(dut.hart.MemRWM[1]) begin
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// $display("%x, %x, %x, %t", HADDR, dut.PCF, dut.HRDATA, $time);
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end
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end
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logic [`XLEN-1:0] writeDataExpected, writeAdrExpected, writeAdrTranslated;
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// this might need to change
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//always @(HWDATA or HADDR or HSIZE or HWRITE) begin
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always @(negedge HWRITE) begin
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//#1;
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if ($time != 0) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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`ERROR
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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assign writeAdrTranslated = adrTranslator(writeAdrExpected);
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if (writeDataExpected != HWDATA) begin
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$display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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`ERROR
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end
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if (~equal(writeAdrTranslated,HADDR,1)) begin
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$display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrTranslated);
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`ERROR
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end
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end
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end
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integer totalCSR = 0;
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logic [99:0] StartCSRexpected[63:0];
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string StartCSRname[99:0];
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initial begin
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while(1) begin
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scan_file_csr = $fscanf(data_file_csr, "%s\n", StartCSRname[totalCSR]);
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if(StartCSRname[totalCSR] == "---") begin
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break;
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end
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scan_file_csr = $fscanf(data_file_csr, "%x\n", StartCSRexpected[totalCSR]);
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totalCSR = totalCSR + 1;
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end
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end
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always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
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if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin
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$display("!!!!!! illegal instruction !!!!!!!!!!");
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$display("(as a reminder, MCAUSE and MEPC are set by this)");
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$display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
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`ERROR
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end
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if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin
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$display("!!!!!! illegal (physical) memory access !!!!!!!!!!");
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$display("(as a reminder, MCAUSE and MEPC are set by this)");
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$display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
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`ERROR
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end
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end
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`define CHECK_CSR2(CSR, PATH) \
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string CSR; \
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logic [63:0] expected``CSR``; \
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//CSR checking \
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always @(``PATH``.``CSR``_REGW) begin \
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if ($time > 1) begin \
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if ("SEPC" == `"CSR`") begin #1; end \
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if ("SCAUSE" == `"CSR`") begin #2; end \
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if ("SSTATUS" == `"CSR`") begin #3; end \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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if(CSR.icompare(`"CSR`")) begin \
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$display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
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end \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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`ERROR \
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end \
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end else begin \
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if (!(`BUILDROOT == 1 && "MSTATUS" == `"CSR`")) begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(`"CSR`")) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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`ERROR \
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end \
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end \
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end \
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end \
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end \
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end
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`define CHECK_CSR(CSR) \
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`CHECK_CSR2(CSR, dut.hart.priv.csr)
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`define CSRM dut.hart.priv.csr.genblk1.csrm
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`define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1
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//`CHECK_CSR(FCSR)
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`CHECK_CSR2(MCAUSE, `CSRM)
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`CHECK_CSR(MCOUNTEREN)
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`CHECK_CSR(MEDELEG)
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`CHECK_CSR(MEPC)
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//`CHECK_CSR(MHARTID)
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`CHECK_CSR(MIDELEG)
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`CHECK_CSR(MIE)
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//`CHECK_CSR(MIP)
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`CHECK_CSR2(MISA, `CSRM)
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`CHECK_CSR2(MSCRATCH, `CSRM)
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`CHECK_CSR(MSTATUS)
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`CHECK_CSR2(MTVAL, `CSRM)
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`CHECK_CSR(MTVEC)
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//`CHECK_CSR2(PMPADDR0, `CSRM)
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//`CHECK_CSR2(PMdut.PCFG0, `CSRM)
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`CHECK_CSR(SATP)
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`CHECK_CSR2(SCAUSE, `CSRS)
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`CHECK_CSR(SCOUNTEREN)
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`CHECK_CSR(SEPC)
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`CHECK_CSR(SIE)
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`CHECK_CSR2(SSCRATCH, `CSRS)
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`CHECK_CSR(SSTATUS)
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`CHECK_CSR2(STVAL, `CSRS)
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`CHECK_CSR(STVEC)
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//$stop;
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generate
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if (`BUSYBEAR == 1) begin
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initial begin //this is temporary until the bug can be fixed!!!
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#11130100;
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force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004;
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#100;
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release dut.hart.ieu.dp.regf.rf[5];
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end
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end
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endgenerate
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logic speculative;
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initial begin
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speculative = 0;
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end
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logic [63:0] lastCheckInstrD, lastPC, lastPC2;
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string PCtextW, PCtext2W;
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logic [31:0] InstrWExpected;
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logic [63:0] PCWExpected;
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always @(PCW or dut.hart.ieu.InstrValidW) begin
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if(dut.hart.ieu.InstrValidW && PCW != 0) begin
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if($feof(data_file_PCW)) begin
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$display("no more PC data to read");
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|
`ERROR
|
|
end
|
|
scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW);
|
|
PCtext2W = "";
|
|
while (PCtext2W != "***") begin
|
|
PCtextW = {PCtextW, " ", PCtext2W};
|
|
scan_file_PC = $fscanf(data_file_PCW, "%s\n", PCtext2W);
|
|
end
|
|
scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected);
|
|
// then expected PC value
|
|
scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
|
|
if(~equal(PCW,PCWExpected,2)) begin
|
|
$display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, PCW, PCWExpected);
|
|
`ERROR
|
|
end
|
|
//if(it.InstrW != InstrWExpected) begin
|
|
// $display("%0t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
|
|
//end
|
|
end
|
|
end
|
|
|
|
string PCtext, PCtext2;
|
|
initial begin
|
|
instrs = 0;
|
|
end
|
|
logic [31:0] InstrMask;
|
|
logic forcedInstr;
|
|
logic [63:0] lastPCD;
|
|
always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin
|
|
if(~HWRITE) begin
|
|
#2;
|
|
if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin
|
|
if (dut.hart.ifu.PCD !== lastPCD) begin
|
|
lastCheckInstrD = CheckInstrD;
|
|
lastPC <= dut.hart.ifu.PCD;
|
|
lastPC2 <= lastPC;
|
|
if (speculative && (lastPC != pcExpected)) begin
|
|
speculative = ~equal(dut.hart.ifu.PCD,pcExpected,3);
|
|
if(dut.hart.ifu.PCD===pcExpected) begin
|
|
if(dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
|
|
force CheckInstrD = 32'b0010011;
|
|
release CheckInstrD;
|
|
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
|
#7;
|
|
release dut.hart.ifu.InstrRawD;
|
|
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
|
|
warningCount += 1;
|
|
forcedInstr = 1;
|
|
end
|
|
else begin
|
|
forcedInstr = 0;
|
|
end
|
|
end
|
|
end
|
|
else begin
|
|
if($feof(data_file_PC)) begin
|
|
$display("no more PC data to read");
|
|
`ERROR
|
|
end
|
|
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
|
|
PCtext2 = "";
|
|
while (PCtext2 != "***") begin
|
|
PCtext = {PCtext, " ", PCtext2};
|
|
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
|
|
end
|
|
scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
|
|
if(dut.hart.ifu.PCD === pcExpected) begin
|
|
if(dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
|
|
force CheckInstrD = 32'b0010011;
|
|
release CheckInstrD;
|
|
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
|
#7;
|
|
release dut.hart.ifu.InstrRawD;
|
|
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
|
|
warningCount += 1;
|
|
forcedInstr = 1;
|
|
end
|
|
else begin
|
|
forcedInstr = 0;
|
|
end
|
|
end
|
|
// then expected PC value
|
|
scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
|
|
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
|
|
(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
|
|
(instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
|
|
$display("loaded %0d instructions", instrs);
|
|
end
|
|
instrs += 1;
|
|
// are we at a branch/jump?
|
|
casex (lastCheckInstrD[31:0])
|
|
32'b00000000001000000000000001110011, // URET
|
|
32'b00010000001000000000000001110011, // SRET
|
|
32'b00110000001000000000000001110011, // MRET
|
|
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
|
|
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
|
|
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
|
|
32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
|
|
32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
|
|
32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
|
|
speculative = 1;
|
|
32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
|
|
32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
|
|
speculative = 0; // tbh don't really know what should happen here
|
|
32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
|
|
32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
|
|
32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
|
|
speculative = 1;
|
|
default:
|
|
speculative = 0;
|
|
endcase
|
|
|
|
//check things!
|
|
if ((~speculative) && (~equal(dut.hart.ifu.PCD,pcExpected,3))) begin
|
|
$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, pcExpected);
|
|
`ERROR
|
|
end
|
|
InstrMask = CheckInstrD[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
|
|
if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrRawD) !== (InstrMask & CheckInstrD))) begin
|
|
$display("%0t ps, instr %0d: InstrD does not equal CheckInstrD: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrRawD, CheckInstrD, dut.hart.ifu.PCD);
|
|
`ERROR
|
|
end
|
|
end
|
|
end
|
|
lastPCD = dut.hart.ifu.PCD;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Track names of instructions
|
|
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
|
logic [31:0] InstrW;
|
|
instrTrackerTB it(clk, reset,
|
|
dut.hart.ifu.icache.controller.FinalInstrRawF,
|
|
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
|
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
|
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
|
|
|
// generate clock to sequence tests
|
|
always
|
|
begin
|
|
clk <= 1; # 5; clk <= 0; # 5;
|
|
end
|
|
|
|
endmodule
|
|
module instrTrackerTB(
|
|
input logic clk, reset,
|
|
input logic [31:0] InstrF,InstrD,InstrE,InstrM,InstrW,
|
|
output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
|
|
|
// stage Instr to Writeback for visualization
|
|
//flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
|
|
|
instrNameDecTB fdec(InstrF, InstrFName);
|
|
instrNameDecTB ddec(InstrD, InstrDName);
|
|
instrNameDecTB edec(InstrE, InstrEName);
|
|
instrNameDecTB mdec(InstrM, InstrMName);
|
|
instrNameDecTB wdec(InstrW, InstrWName);
|
|
endmodule
|
|
|
|
// decode the instruction name, to help the test bench
|
|
module instrNameDecTB(
|
|
input logic [31:0] instr,
|
|
output string name);
|
|
|
|
logic [6:0] op;
|
|
logic [2:0] funct3;
|
|
logic [6:0] funct7;
|
|
logic [11:0] imm;
|
|
|
|
assign op = instr[6:0];
|
|
assign funct3 = instr[14:12];
|
|
assign funct7 = instr[31:25];
|
|
assign imm = instr[31:20];
|
|
|
|
// it would be nice to add the operands to the name
|
|
// create another variable called decoded
|
|
|
|
always_comb
|
|
casez({op, funct3})
|
|
10'b0000000_000: name = "BAD";
|
|
10'b0000011_000: name = "LB";
|
|
10'b0000011_001: name = "LH";
|
|
10'b0000011_010: name = "LW";
|
|
10'b0000011_011: name = "LD";
|
|
10'b0000011_100: name = "LBU";
|
|
10'b0000011_101: name = "LHU";
|
|
10'b0000011_110: name = "LWU";
|
|
10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
|
|
else name = "ADDI";
|
|
10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
|
|
else name = "ILLEGAL";
|
|
10'b0010011_010: name = "SLTI";
|
|
10'b0010011_011: name = "SLTIU";
|
|
10'b0010011_100: name = "XORI";
|
|
10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
|
|
else if (funct7[6:1] == 6'b010000) name = "SRAI";
|
|
else name = "ILLEGAL";
|
|
10'b0010011_110: name = "ORI";
|
|
10'b0010011_111: name = "ANDI";
|
|
10'b0010111_???: name = "AUIPC";
|
|
10'b0100011_000: name = "SB";
|
|
10'b0100011_001: name = "SH";
|
|
10'b0100011_010: name = "SW";
|
|
10'b0100011_011: name = "SD";
|
|
10'b0011011_000: name = "ADDIW";
|
|
10'b0011011_001: name = "SLLIW";
|
|
10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
|
|
else if (funct7 == 7'b0100000) name = "SRAIW";
|
|
else name = "ILLEGAL";
|
|
10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
|
|
else if (funct7 == 7'b0100000) name = "SUBW";
|
|
else name = "ILLEGAL";
|
|
10'b0111011_001: name = "SLLW";
|
|
10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
|
|
else if (funct7 == 7'b0100000) name = "SRAW";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
|
|
else if (funct7 == 7'b0000001) name = "MUL";
|
|
else if (funct7 == 7'b0100000) name = "SUB";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
|
|
else if (funct7 == 7'b0000001) name = "MULH";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
|
|
else if (funct7 == 7'b0000001) name = "MULHSU";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
|
|
else if (funct7 == 7'b0000001) name = "DIV";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
|
|
else if (funct7 == 7'b0000001) name = "MUL";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
|
|
else if (funct7 == 7'b0000001) name = "DIVU";
|
|
else if (funct7 == 7'b0100000) name = "SRA";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
|
|
else if (funct7 == 7'b0000001) name = "REM";
|
|
else name = "ILLEGAL";
|
|
10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
|
|
else if (funct7 == 7'b0000001) name = "REMU";
|
|
else name = "ILLEGAL";
|
|
10'b0110111_???: name = "LUI";
|
|
10'b1100011_000: name = "BEQ";
|
|
10'b1100011_001: name = "BNE";
|
|
10'b1100011_100: name = "BLT";
|
|
10'b1100011_101: name = "BGE";
|
|
10'b1100011_110: name = "BLTU";
|
|
10'b1100011_111: name = "BGEU";
|
|
10'b1100111_000: name = "JALR";
|
|
10'b1101111_???: name = "JAL";
|
|
10'b1110011_000: if (imm == 0) name = "ECALL";
|
|
else if (imm == 1) name = "EBREAK";
|
|
else if (imm == 2) name = "URET";
|
|
else if (imm == 258) name = "SRET";
|
|
else if (imm == 770) name = "MRET";
|
|
else name = "ILLEGAL";
|
|
10'b1110011_001: name = "CSRRW";
|
|
10'b1110011_010: name = "CSRRS";
|
|
10'b1110011_011: name = "CSRRC";
|
|
10'b1110011_101: name = "CSRRWI";
|
|
10'b1110011_110: name = "CSRRSI";
|
|
10'b1110011_111: name = "CSRRCI";
|
|
10'b0001111_???: name = "FENCE";
|
|
default: name = "ILLEGAL";
|
|
endcase
|
|
endmodule
|
|
|