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105 lines
3.7 KiB
Systemverilog
105 lines
3.7 KiB
Systemverilog
`include "wally-config.vh"
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module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, parameter WORDSIZE = `XLEN) (
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// Pipeline stuff
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input logic clk,
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input logic reset,
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// If flush is high, invalidate the entire cache
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input logic flush,
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// Select which address to read (broken for efficiency's sake)
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input logic [`XLEN-1:0] PCTagF, // physical tag address
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input logic [`XLEN-1:0] PCNextIndexF,
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// Write new data to the cache
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input logic WriteEnable,
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input logic [LINESIZE-1:0] WriteLine,
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// Output the word, as well as if it is valid
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output logic [31:0] DataWord, // *** was WORDSIZE-1
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output logic DataValid
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);
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// Various compile-time constants
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localparam integer WORDWIDTH = $clog2(WORDSIZE/8);
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localparam integer OFFSETWIDTH = $clog2(LINESIZE/WORDSIZE);
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localparam integer SETWIDTH = $clog2(NUMLINES);
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localparam integer TAGWIDTH = `XLEN - OFFSETWIDTH - SETWIDTH - WORDWIDTH;
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localparam integer OFFSETBEGIN = WORDWIDTH;
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localparam integer OFFSETEND = OFFSETBEGIN+OFFSETWIDTH-1;
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localparam integer SETBEGIN = OFFSETEND+1;
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localparam integer SETEND = SETBEGIN + SETWIDTH - 1;
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localparam integer TAGBEGIN = SETEND + 1;
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localparam integer TAGEND = TAGBEGIN + TAGWIDTH - 1;
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// Machinery to read from and write to the correct addresses in memory
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logic [LINESIZE-1:0] ReadLine;
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logic [LINESIZE/WORDSIZE-1:0][WORDSIZE-1:0] ReadLineTransformed;
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// Machinery to check if a given read is valid and is the desired value
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logic [TAGWIDTH-1:0] DataTag;
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logic [NUMLINES-1:0] ValidOut;
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logic DataValidBit;
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// Depth is number of bits in one "word" of the memory, width is number of such words
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sram1rw #(.DEPTH(LINESIZE), .WIDTH(NUMLINES)) cachemem (
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.*,
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.Addr(PCNextIndexF[SETEND:SETBEGIN]),
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.ReadData(ReadLine),
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.WriteData(WriteLine)
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);
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sram1rw #(.DEPTH(TAGWIDTH), .WIDTH(NUMLINES)) cachetags (
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.*,
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.Addr(PCNextIndexF[SETEND:SETBEGIN]),
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.ReadData(DataTag),
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.WriteData(PCTagF[TAGEND:TAGBEGIN])
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);
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// Pick the right bits coming out the read line
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//assign DataWord = ReadLineTransformed[ReadOffset];
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//logic [31:0] tempRD;
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always_comb begin
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case (PCTagF[4:1])
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0: DataWord = ReadLine[31:0];
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1: DataWord = ReadLine[47:16];
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2: DataWord = ReadLine[63:32];
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3: DataWord = ReadLine[79:48];
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4: DataWord = ReadLine[95:64];
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5: DataWord = ReadLine[111:80];
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6: DataWord = ReadLine[127:96];
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7: DataWord = ReadLine[143:112];
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8: DataWord = ReadLine[159:128];
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9: DataWord = ReadLine[175:144];
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10: DataWord = ReadLine[191:160];
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11: DataWord = ReadLine[207:176];
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12: DataWord = ReadLine[223:192];
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13: DataWord = ReadLine[239:208];
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14: DataWord = ReadLine[255:224];
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15: DataWord = {16'b0, ReadLine[255:240]};
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endcase
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end
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genvar i;
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generate
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for (i=0; i < LINESIZE/WORDSIZE; i++) begin
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assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE];
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end
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endgenerate
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// Correctly handle the valid bits
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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ValidOut <= {NUMLINES{1'b0}};
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end else if (flush) begin
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ValidOut <= {NUMLINES{1'b0}};
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end else begin
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if (WriteEnable) begin
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ValidOut[PCNextIndexF[SETEND:SETBEGIN]] <= 1;
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end
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end
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DataValidBit <= ValidOut[PCNextIndexF[SETEND:SETBEGIN]];
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end
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assign DataValid = DataValidBit && (DataTag == PCTagF[TAGEND:TAGBEGIN]);
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endmodule
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