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https://github.com/openhwgroup/cvw
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Since writing an SD card image generation script, the bootloader needed to be altered to access individual binaries from specific partitions. A new file, gpt.c with it's header gpt.h, have been added to the bootloader to facilitate this. The SDC has been added to the device tree for the VCU108 board. Additionally the SDC interrupt signal was added to the PLIC node in the device tree. The PLIC itself was modified to accept the SDC interrupt signal.
203 lines
9.0 KiB
Systemverilog
203 lines
9.0 KiB
Systemverilog
///////////////////////////////////////////
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// uncore.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified: Ben Bracker 6 Mar 2021 to better fit AMBA 3 AHB-Lite spec
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//
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// Purpose: System-on-Chip components outside the core
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// Memories, peripherals, external bus control
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//
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// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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// *** need idiom to map onto cache RAM with byte writes
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// *** and use memread signal to reduce power when reads aren't needed
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module uncore (
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// AHB Bus Interface
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input logic HCLK, HRESETn,
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input logic TIMECLK,
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input logic [`PA_BITS-1:0] HADDR,
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input logic [`AHBW-1:0] HWDATA,
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input logic [`XLEN/8-1:0] HWSTRB,
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input logic HWRITE,
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input logic [2:0] HSIZE,
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input logic [2:0] HBURST,
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input logic [3:0] HPROT,
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input logic [1:0] HTRANS,
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input logic HMASTLOCK,
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input logic [`AHBW-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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output logic [`AHBW-1:0] HRDATA,
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output logic HREADY, HRESP,
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output logic HSELEXT,
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output logic HSELEXTSDC,
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// peripheral pins
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output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT
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output logic MExtInt, SExtInt, // External interrupts from PLIC
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output logic [63:0] MTIME_CLINT, // MTIME, from CLINT
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input logic [31:0] GPIOPinsIn, // GPIO pin input value
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output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable
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input logic UARTSin, // UART serial input
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output logic UARTSout, // UART serial output
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input logic SDCIntr
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/*output logic SDCCmdOut, // SD Card command output
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output logic SDCCmdOE, // SD Card command output enable
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input logic SDCCmdIn, // SD Card command input
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input logic [3:0] SDCDatIn, // SD Card data input
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output logic SDCCLK // SD Card clock*/
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);
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logic [`XLEN-1:0] HREADRam, HREADSDC;
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logic [11:0] HSELRegions;
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logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
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logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
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logic HRESPRam, HRESPSDC;
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logic HREADYRam, HRESPSDCD;
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logic [`XLEN-1:0] HREADBootRom;
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logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
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logic HSELNoneD;
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logic UARTIntr,GPIOIntr;
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logic SDCIntM;
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logic PCLK, PRESETn, PWRITE, PENABLE;
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logic [3:0] PSEL, PREADY;
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logic [31:0] PADDR;
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logic [`XLEN-1:0] PWDATA;
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logic [`XLEN/8-1:0] PSTRB;
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logic [3:0][`XLEN-1:0] PRDATA;
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logic [`XLEN-1:0] HREADBRIDGE;
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logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
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(* mark_debug = "true" *) logic HSELEXTSDCD;
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// Determine which region of physical memory (if any) is being accessed
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// Use a trimmed down portion of the PMA checker - only the address decoders
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// Set access types to all 1 as don't cares because the MMU has already done access checking
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adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
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// unswizzle HSEL signals
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assign {HSELEXTSDC, HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[11:1];
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// AHB -> APB bridge
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ahbapbbridge #(4) ahbapbbridge (
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.HCLK, .HRESETn, .HSEL({HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY,
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.HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
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.PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
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assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART; // if any of the bridge signals are selected
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// on-chip RAM
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if (`UNCORE_RAM_SUPPORTED) begin : ram
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ram_ahb #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram (
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.HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY,
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.HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
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end
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if (`BOOTROM_SUPPORTED) begin : bootrom
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rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
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bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS,
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.HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
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end
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// memory-mapped I/O peripherals
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if (`CLINT_SUPPORTED == 1) begin : clint
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clint_apb clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
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.PRDATA(PRDATA[1]), .PREADY(PREADY[1]), .MTIME(MTIME_CLINT), .MTimerInt, .MSwInt);
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end else begin : clint
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assign MTIME_CLINT = 0;
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assign MTimerInt = 0; assign MSwInt = 0;
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end
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if (`PLIC_SUPPORTED == 1) begin : plic
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plic_apb plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
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.PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .SDCIntr, .MExtInt, .SExtInt);
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end else begin : plic
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assign MExtInt = 0;
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assign SExtInt = 0;
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end
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if (`GPIO_SUPPORTED == 1) begin : gpio
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gpio_apb gpio(
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.PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
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.PRDATA(PRDATA[0]), .PREADY(PREADY[0]),
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.iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr);
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end else begin : gpio
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assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
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end
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if (`UART_SUPPORTED == 1) begin : uart
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uart_apb uart(
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.PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
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.PRDATA(PRDATA[3]), .PREADY(PREADY[3]),
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.SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
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.SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface
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.OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU
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end else begin : uart
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assign UARTSout = 0; assign UARTIntr = 0;
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end
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/*if (`SDC_SUPPORTED == 1) begin : sdc
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SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
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.HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
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// sdc interface
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.SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
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// interrupt to PLIC
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.SDCIntM
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);
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end else begin : sdc
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assign SDCCLK = 0;
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assign SDCCmdOut = 0;
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assign SDCCmdOE = 0;
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end
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*/
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// AHB Read Multiplexer
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assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
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({`XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) |
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({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
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({`XLEN{HSELBootRomD}} & HREADBootRom) |
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({`XLEN{HSELSDCD}} & HREADSDC);
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assign HRESP = HSELRamD & HRESPRam |
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(HSELEXTD | HSELEXTSDCD) & HRESPEXT |
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HSELBRIDGE & HRESPBRIDGE |
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HSELBootRomD & HRESPBootRom |
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HSELSDC & HRESPSDC;
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assign HREADY = HSELRamD & HREADYRam |
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(HSELEXTD | HSELEXTSDCD) & HREADYEXT |
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HSELBRIDGED & HREADYBRIDGE |
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HSELBootRomD & HREADYBootRom |
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HSELSDCD & HREADYSDC |
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HSELNoneD; // don't lock up the bus if no region is being accessed
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// Address Decoder Delay (figure 4-2 in spec)
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// The select for HREADY needs to be based on the address phase address. If the device
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// takes more than 1 cycle to repsond it needs to hold on to the old select until the
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// device is ready. Hense this register must be selectively enabled by HREADY.
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// However on reset None must be seleted.
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flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[11:0], 11'b1, {HSELEXTSDCD, HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
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flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
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endmodule
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