mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
46 lines
2.1 KiB
Bash
Executable File
46 lines
2.1 KiB
Bash
Executable File
#!/bin/bash
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# this script is used to run regression inside the Dockerfile.regression
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# of course, you can run it in the current environment as soon as
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# - RISCV is defined
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# - QUESTA is defined
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export QUESTA="/cad/mentor/questa_sim-xxxx.x_x"
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export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemons license server
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export SNPSLMD_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Synopsys license server
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export QUESTAPATH=/cad/mentor/questa_sim-xxxx.x_x/questasim/bin # Change this for your path to Questa
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export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
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# now only main branch is supported
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if [ -z "${CVW_GIT}" ]; then
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echo "No CVW_GIT is provided"
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CVW_GIT="https://github.com/openhwgroup/cvw"
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fi
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export PATH="${RISCV}/bin:${PATH}"
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git config --global http.version HTTP/1.1
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# if cvw is not available or CLEAN_CVW(empty string) is defined
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if [[ ! -f "/home/${USERNAME}/cvw/setup.sh" ]] || [[ -z "${CLEAN_CVW-x}" ]]; then
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cd /home/${USERNAME} && rm -rf /home/${USERNAME}/cvw
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git clone --recurse-submodules ${CVW_GIT} /home/${USERNAME}/cvw
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# if failed to clone submodules for some reason, please run `git submodule update`
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fi
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cd /home/${USERNAME}/cvw && chmod +x ./setup.sh && ./setup.sh
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# build it only if BUILD_RISCOF is defined with empty string
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if [[ -z "${BUILD_RISCOF-x}" ]]; then
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make install && make riscof && make testfloat
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fi
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if [[ -z "${RUN_QUESTA-x}" ]] ; then
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if [ ! -f "${QUESTA}/questasim/bin/vsim" ]; then
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echo "Cannot find vsim with ${QUESTA}/questasim/bin/vsim"
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else
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export PATH="${QUESTA}/questasim/bin:${PATH}"
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cd sim && ./regression-wally 2>&1 > ./regression_questa.out && cd ..
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fi
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fi
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cd sim && verilator -GTEST="\"arch64i\"" -DVERILATOR=1 --timescale "1ns/1ns" --timing --binary --top-module testbench -I../config/shared -I../config/rv64gc ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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/home/${USERNAME}/cvw/sim/obj_dir/Vtestbench > ./regression_verilator.out
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