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72 lines
3.4 KiB
Systemverilog
72 lines
3.4 KiB
Systemverilog
///////////////////////////////////////////
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// imem.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose:
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module imem (
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input logic [`XLEN-1:1] AdrF,
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output logic [31:0] InstrF,
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output logic [15:0] rd2, // bogus, delete when real multicycle fetch works
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output logic InstrAccessFaultF);
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/* verilator lint_off UNDRIVEN */
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logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)];
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logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
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/* verilator lint_on UNDRIVEN */
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logic [31:0] adrbits; // needs to be 32 bits to index RAM
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logic [`XLEN-1:0] rd;
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// logic [15:0] rd2;
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generate
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if (`XLEN==32) assign adrbits = AdrF[31:2];
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else assign adrbits = AdrF[31:3];
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endgenerate
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assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
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// hack right now for unaligned 32-bit instructions
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// eventually this will need to cause a stall like a cache miss
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// when the instruction wraps around a cache line
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// could be optimized to only stall when the instruction wrapping is 32 bits
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assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
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generate
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if (`XLEN==32) begin
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assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
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// First, AdrF needs to get its last bit appended back onto it
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// Then not-XORing it with TIMBASE checks if it matches TIMBASE exactly
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// Then ORing it with TIMRANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low
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assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIMBASE) | `TIMRANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIMBASE) | `BOOTTIMRANGE));
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end else begin
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assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
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: (AdrF[1] ? rd[47:16] : rd[31:0]);
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//
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assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIMBASE | `BOOTTIMRANGE));
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end
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endgenerate
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endmodule
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