mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
98 lines
3.2 KiB
Python
Executable File
98 lines
3.2 KiB
Python
Executable File
#!/usr/bin/python3
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###########################################
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## fpgaTop.sv
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##
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## Written: jacob.pease@okstate.edu 06 April 2023
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## Modified:
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##
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## Purpose: Generates 1 entry in a ILA debugger
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##
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## A component of the Wally configurable RISC-V project.
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##
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## Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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##
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## Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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## files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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## modify, merge, publish, distribute, sublicense, and#or sell copies of the Software, and to permit persons to whom the Software
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## is furnished to do so, subject to the following conditions:
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##
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## The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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##
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## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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## OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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## OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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###########################################
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import sys
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def usage():
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print("Usage: ./probes name width probenum")
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def header():
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return """create_debug_core u_ila_0 ila
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set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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startgroup
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
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set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
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set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
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endgroup
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connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""
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def convertLine(x):
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temp = x.split()
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temp[1] = int(temp[1])
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return tuple(temp)
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def probeBits( probe ):
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str = ''
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if (probe[1] > 1):
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for i in range(probe[1]):
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if i != (probe[1]-1):
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str = str + f"{{{probe[0]}[{i}]}} "
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else:
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str = str + f"{{{probe[0]}[{i}]}} "
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else:
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str = f'{{{probe[0]}}}'
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return str
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def printProbe( probe, i ):
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bits = probeBits(probe)
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return (
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f'create_debug_port u_ila_0 probe\n'
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f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
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f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
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f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
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)
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def main(args):
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if (len(args) != 3):
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usage()
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name = args[0]
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width = int(args[1])
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probeNum = int(args[2])
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probe = (name, width)
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print(printProbe(probe, probeNum))
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if __name__ == '__main__':
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main(sys.argv[1:])
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