cvw/wally-pipelined/src
2021-05-31 11:01:15 -04:00
..
cache
dmem
ebu
fpu classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
generic Modify elements of generics for LZD and shifter wrote for integer 2021-05-31 08:36:19 -04:00
hazard turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
ieu
ifu turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
mmu made priority encoder parameterizable 2021-05-28 18:09:28 -04:00
muldiv Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
privileged turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
uncore
wally turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00