mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
327 lines
6.8 KiB
ArmAsm
327 lines
6.8 KiB
ArmAsm
///////////////////////////////////////////
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// priv.S
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//
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// Written: David_Harris@hmc.edu 23 March 2023
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//
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// Purpose: Test coverage for EBU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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# Tests sret in machine mode
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la t1, sretdone
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csrw sepc, t1
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sret
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sretdone:
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addi t2, x0, 42
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# switch to user mode
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li a0, 0
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ecall
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sret #should be treated as illegal instruction
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mret #mret in user mode and should be illegal
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# switch to supervisor mode
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li a0, 1
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ecall
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# Test read to stimecmp fails when MCOUNTEREN_TM is not set
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li t1, -3
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csrw stimecmp, t1
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csrr t0, stimecmp
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# satp write with mstatus.TVM = 1
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bseti t0, zero, 20
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csrs mstatus, t0
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csrw satp, zero
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# STIMECMP from S mode
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# 1st is when MENVCFG_STCE is cleared
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li a0, 3
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ecall # starts in M-mode
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li t1, -3
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csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately
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li t0, 2
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csrs mstatus, t0 # enables sie
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li t0, 32
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csrs sie, t0 # enables sie.stie
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csrw menvcfg, x0
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li a0, 1
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ecall # enter S-mode
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csrw stimecmp, zero
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li a0, 3
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ecall # in M-mode
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li t0, 32
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csrs mip, t0
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li a0, 1
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ecall # in S-mode and expects stimer interrupt to occur
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li a0, 3
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ecall # return to M-mode
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csrsi mcounteren, 2 # mcounteren_tm = 1
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li a0, 1
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ecall # supervisor mode again
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csrw stimecmp, zero
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li a0, 3
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ecall # machine mode again
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# STIMECMP from S mode
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# 2nd is when MENVCFG_STCE is set
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csrci mcounteren, 2 # mcounteren_tm = 0
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li t0, 1
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slli t0, t0, 63
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csrw menvcfg, t0
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li a0, 1
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ecall # enter S-mode
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csrw stimecmp, zero
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li a0, 3
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ecall # return to M-mode
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csrsi mcounteren, 2 # mcounteren_tm = 1
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li a0, 1
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ecall # supervisor mode again
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csrw stimecmp, zero
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li a0, 3
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ecall # machine mode again
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# writes to FCSR
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li t0, 1
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slli t0, t0, 13
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csrs mstatus, t0
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li t0, 1
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csrw fcsr, t0
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# switch to supervisor mode
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li a0, 1
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ecall
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# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
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li t0, 0
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csrw stval, t0
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csrw scause, t0
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csrw sepc, t0
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csrw stimecmp, t0
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csrw scounteren, zero
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csrw satp, zero
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# Switch to machine mode
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li a0, 3
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ecall
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# Write to MCOUNTINHIBIT CSR
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csrw mcountinhibit, t0
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# Testing the HPMCOUNTERM performance counter: writing
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# Base address is 2816 (MHPMCOUNTERBASE)
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# There are 32 HPMCOUNTER registers
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csrw 2816, t0
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csrw 2817, t0
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csrw 2818, t0
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csrw 2819, t0
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csrw 2820, t0
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csrw 2821, t0
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csrw 2822, t0
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csrw 2823, t0
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csrw 2824, t0
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csrw 2825, t0
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csrw 2826, t0
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csrw 2827, t0
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csrw 2828, t0
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csrw 2829, t0
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csrw 2830, t0
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csrw 2831, t0
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csrw 2832, t0
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csrw 2833, t0
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csrw 2834, t0
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csrw 2835, t0
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csrw 2836, t0
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csrw 2837, t0
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csrw 2838, t0
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csrw 2839, t0
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csrw 2840, t0
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csrw 2841, t0
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csrw 2842, t0
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csrw 2843, t0
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csrw 2844, t0
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csrw 2845, t0
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csrw 2846, t0
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csrw 2847, t0
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# Testing the HPMCOUNTERM performance counter: reading
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csrr t0, 2817
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# Test writes to pmp address registers
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csrw 951, t0
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csrw 952, t0
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csrw 953, t0
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csrw 954, t0
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csrw 955, t0
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csrw 956, t0
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csrw 957, t0
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csrw 958, t0
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# Testing writes to MTVAL, MCAUSE
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li t0, 0
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csrw mtval, t0
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csrw mcause, t0
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# set mstatus to enable floating point registers (mstatus.FS = 11)
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bseti t1, zero, 13
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csrs mstatus, t1
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bseti t1, zero, 14
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csrs mstatus, t1
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# Test writes to floating point CSRs
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csrw frm, t0
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csrw fflags, t0
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# CSRC MCOUNTEREN Register
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# Go to machine mode
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li a0, 3
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ecall
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# Activate HPM3
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li t0, -1
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csrw mcounteren, t0
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csrw scounteren, t0
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# Go to supervisor
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li a0, 1
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ecall
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#try to write to HPMs
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csrw 333, t0
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#go to user mode
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li a0, 0
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ecall
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csrr t0, hpmcounter22
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# setting registers bits to 0
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li a0, 3 # back to machine mode
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ecall
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li t0, 0
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csrw mcounteren, t0
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csrw scounteren, t0
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#getting the remainder of PMD instructions
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#go to user mode
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li a0, 0
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ecall
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#set status TVM to 0 by writing to bit 20 of mstatus as 0
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#bseti t0, zero, 20
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sfence.vma zero, zero
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# Go to supervisor mode
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li a0, 1
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ecall
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sfence.vma zero, zero
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li a0, 3
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ecall
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# Write to satp when status.TVM is 1 from machine mode
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bseti t0, zero, 20
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csrs mstatus, t0
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csrw satp, t0
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# Test checking privilege for reading counters (using counter 22 as an example)
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# Go to machine mode
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li a0, 3
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ecall
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# Set SCOUNTEREN to all 0s, MCOUNTEREN to all 1s
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li t0, 0
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csrw scounteren, t0
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li t1, -1
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csrw mcounteren, t1
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# Go to supervisor mode
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li a0, 1
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ecall
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# try to read from HPM22
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csrr t0, hpmcounter22
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# go to user mode
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li a0, 0
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ecall
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csrr t0, hpmcounter22
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#getting the mpp and mstatus Mpriv condition met
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#go to machine mode
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li a0, 3
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ecall
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# set bit 17 of mstatus to enable STATUS_MPRV
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bseti t1, zero, 17
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csrs mstatus, t1
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li a0, 3
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ecall
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# set bit 21 of mstatus to 0 to disable STATUS_TW
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csrr t1, mstatus
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bseti t2, zero, 21
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not t2, t2
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and t1, t1, t2
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csrs mstatus, t1
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# go to user mode
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li a0, 0
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ecall
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wfi
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# Test uncovered privdec instructions
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li a0, 3
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ecall
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# exercise sfence.inval.ir instruction
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.word 0x18100073
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# exercise sret with rs1 not 0
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.word 0x102F8073
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# cover mret when mpp = 3 and mprv = 1
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li a0, 3
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ecall # enter machine mode
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bseti t0, zero, 17
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csrs mstatus, t0 # set MPRV
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li t1, 0x00001800
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csrs mstatus, t1 # set MPP=3
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la t1, finished
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csrr t0, mepc
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csrw mepc, t1 # set mepc for mret to jump to
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mret
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finished: j done
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