mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
220 lines
7.7 KiB
ArmAsm
220 lines
7.7 KiB
ArmAsm
///////////////////////////////////////////
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// fpu.S
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//
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// Written: David_Harris@hmc.edu 28 March 2023
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//
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// Purpose: Test coverage for FPU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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bseti t0, zero, 14 # turn on FPU
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csrs mstatus, t0
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#Pull denormalized FP number from memory and pass it to fclass.S for coverage
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la t0, TestData1
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flw ft0, 0(t0)
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fclass.s t1, ft0
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# zfa instructions (because Zfa tests aren't running yet)
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fli.d fs0, 16
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fcvtmod.w.d t0, fs0, rtz
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# fminm.d fs1, fs0, fs0
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# fmaxm.d fs1, fs0, fs0
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# fltq.d t0, fs1, ft0
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# fleq.d t0, fs1, ft0
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fcvt.d.q fs1, fs0
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fcvt.h.q fs1, fs0
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fcvt.s.q fs1, fs0
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# round for now because these tests are excluded from Zfa until rounding is implemented
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fround.s fs1, fs0
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froundnx.s fs1, fs0
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fround.d fs1, fs0
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froundnx.d fs1, fs0
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fround.h fs1, fs0
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froundnx.h fs1, fs0
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fround.s fs1, fs0
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froundnx.s fs1, fs0
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#Result Sign Test Coverage
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la t0, TestData2
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flw ft0, 0(t0)
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flw ft1, 4(t0)
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fadd.s ft2, ft0, ft1 #Adds coverage for inf as arg for FADD
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flw ft2, 4(t0)
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fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit
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#Adds Coverage for Flag fmaAs, fmaPs, YSNaN, ZSNaN
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fmadd.s ft3, ft0, ft1, ft2
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flw ft0, 8(t0)
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fmadd.s ft3, ft0, ft1, ft2
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flw ft1, 12(t0)
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fmadd.s ft3, ft0, ft1, ft2
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flw ft2, 12(t0)
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flw ft1, 4(t0)
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fmadd.s ft3, ft0, ft1, ft2
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#Add Coverage for round lsbRes
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flw ft0, 16(t0)
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flw ft1, 4(t0)
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fmadd.s ft3, ft0, ft1, ft2
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#Fix BadNaNBox test on unpackinput Z
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la t0, TestData2
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flw ft3, 0(t0)
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flw ft4, 0(t0)
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fadd.s ft5, ft3, ft4
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# Test legal instructions not covered elsewhere
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flq ft0, 0(a0)
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flh ft0, 8(a0)
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fsq ft0, 0(a0)
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fsh ft0, 8(a0)
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# Tests for fpu/fctrl.sv
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fcvt.h.s ft1, ft0
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fcvt.q.s ft2, ft0
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fcvt.h.w ft3, a0
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fcvt.h.wu ft3, a0
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fcvt.h.l ft3, a0
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fcvt.h.lu ft3, a0
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fcvt.w.h a0, ft3
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fcvt.wu.h a0, ft3
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fcvt.l.h a0, ft3
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fcvt.lu.h a0, ft3
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fcvt.q.w ft3, a0
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fcvt.q.wu ft3, a0
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fcvt.q.l ft3, a0
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fcvt.q.lu ft3, a0
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fcvt.w.q a0, ft3
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fcvt.wu.q a0, ft3
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fcvt.l.q a0, ft3
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fcvt.lu.q a0, ft3
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fcvt.l.s a0, ft0
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fcvt.lu.s a0, ft0
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fcvt.s.l ft0, t0
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fcvt.s.lu ft0, t0
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// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
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# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
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// idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc
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# fcvt.h.w ft3, a0
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# fcvt.w.h a0, ft0
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# fcvt.q.w ft3, a0
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# fcvt.w.q a0, ft0
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# fcvt.q.d ft3, ft0
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# half-precision NaN boxing
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la t0, TestData3
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fld ft2, 0(t0) // bad NaN-boxed number
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fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing
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fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing
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// fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives)
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// This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes.
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li t0, 0x3F812345 # random value slightly bigger than 1
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li t1, 0x3F823456
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fmv.w.x ft0, t0 # move int to fp register
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fmv.w.x ft1, t1
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t1, 0x02004000 # MTIMECMP in CLINT
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sd t0, 0(t1)
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csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE
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li t1, 0x0200bff8 # read MTIME in CLINT
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ld t0, 0(t1)
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addi t0, t0, 11
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li t1, 0x02004000 # MTIMECMP in CLINT
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sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency
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nop
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fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush
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csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE
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# Completing branch coverage in fctrl.sv
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.word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011
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.word 0x40000053 // Line 145 All False Test case - illegal instruction?
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.word 0xd0400053 // Line 156 All False Test case - illegal instruction?
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.word 0xc0400053 // Line 162 All False Test case - illegal instruction?
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.word 0xd2400053 // Line 168 All False Test case - illegal instruction?
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.word 0xc2400053 // Line 174 All False Test case - illegal instruction?
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# Increasing conditional coverage in fctrl.sv
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.word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to
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.word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2)
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.word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2)
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.word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl.
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.word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl.
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.word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr
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.word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr
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# Test illegal instructions are detected
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.word 0x00000007 // illegal floating-point load (bad Funct3)
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.word 0x00000027 // illegal floating-point store (bad Funct3)
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.word 0x58F00053 // illegal fsqrt (bad Rs2D)
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.word 0x20007053 // illegal fsgnj (bad Funct3)
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.word 0x28007053 // illegal fmin/max (bad Funct3)
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.word 0xA0007053 // illegal fcmp (bad Funct3)
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.word 0xE0007053 // illegal fclass/fmv (bad Funct3)
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.word 0xF0007053 // illegal fmv (bad Funct3)
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.word 0x43007053 // illegal fcvt.d.* (bad Rs2D)
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.word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1])
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.word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D)
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.word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D)
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.word 0x04000043 // illegal fmadd.h (h not supported)
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.word 0xC2800053 // illegal fcvtmod.w.d with rm rne
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.word 0xF0101053 // illegal fli with Funct3D not 0
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.word 0xF0400053 // illegal fli with Rs2D not 1
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.word 0x44200053 // illegal instruction for f.cvt.h.h
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// Test divide by zero with rounding mode toward zero
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li t0, 1
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csrw frm, t0 // set rounding mode = 1
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li t0, 0x3f800000
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fcvt.s.w ft1, t0
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fcvt.s.w ft2, zero
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fdiv.s ft3, ft1, ft2
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# Test floating point convert to integer and using result
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fcvt.w.s t0, f0
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add t1, t0, t0
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j done
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.section .data
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.align 3
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TestData1:
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.int 0x00100000 #Denormalized FP number
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TestData2:
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.int 0x3f800000 #FP 1.0
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.word 0x7f800000 #INF
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.int 0xbf800000 #FP -1.0
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.int 0x7fa00000 #SNaN
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.int 0x3fffffff #OverFlow Test
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TestData3:
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.dword 0xABCD543212345678 # NaN box test
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DivTestData:
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