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89 lines
3.3 KiB
Systemverilog
89 lines
3.3 KiB
Systemverilog
///////////////////////////////////////////
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// gsharebasic.sv
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//
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// Written: Ross Thompson
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// Email: ross1728@gmail.com
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// Created: 16 March 2021
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// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
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// Modified: 20 February 2023
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module gsharebasic #(parameter k = 10,
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parameter TYPE = 1) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic [1:0] BPDirPredF,
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output logic BPDirPredWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCM,
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input logic BranchE, BranchM, PCSrcE
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);
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logic [k-1:0] IndexNextF, IndexM;
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logic [1:0] BPDirPredD, BPDirPredE;
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logic [1:0] NewBPDirPredE, NewBPDirPredM;
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logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
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logic [k-1:0] GHRNext;
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logic PCSrcM;
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if(TYPE == 1) begin
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assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
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end else if(TYPE == 0) begin
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assign IndexNextF = GHRNext;
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assign IndexM = GHRM;
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end
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(~StallW & ~FlushW),
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.ra1(IndexNextF),
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.rd1(BPDirPredF),
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.wa2(IndexM),
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.wd2(NewBPDirPredM),
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.we2(BranchM),
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.bwe2(1'b1));
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD);
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flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE);
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
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flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
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assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
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assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
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flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
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flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
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flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
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flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
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endmodule
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