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			48 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			Systemverilog
		
	
	
	
	
	
			
		
		
	
	
			48 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			Systemverilog
		
	
	
	
	
	
///////////////////////////////////////////
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// ramxdetector.sv
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//
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// Written: David_Harris@hmc.edu
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// Modified: 2 July 2023
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//
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// Purpose: Detects if the processor is attempting to read unitialized RAM
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// 
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// A component of the Wally configurable RISC-V project.
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// 
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the 
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
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// either express or implied. See the License for the specific language governing permissions 
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ramxdetector #(parameter XLEN, LLEN) (
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  input  logic            clk,
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  input  logic            MemReadM,
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  input  logic            LSULoadAccessFaultM,
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  input  logic [LLEN-1:0] ReadDataM,
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  input  logic [XLEN-1:0] PCM,
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  input  logic [31:0]     InstrM,
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  input  logic [XLEN-1:0] IEUAdrM,
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  input  string           InstrMName
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);
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  always_ff @(posedge clk)
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    /* verilator lint_off WIDTHXZEXPAND */
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    if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
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      /* verilator lint_on WIDTHXZEXPAND */
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      $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests.");
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      $display("  PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
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      //$stop;
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    end
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endmodule
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