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			135 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			Plaintext
		
	
	
		
			Executable File
		
	
	
	
	
			
		
		
	
	
			135 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			Plaintext
		
	
	
		
			Executable File
		
	
	
	
	
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# Search Paths
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set CURRENT_DIR  [exec pwd]
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set search_path [list "./" ]
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set tech $::env(TECH)
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if { [info exists ::env(RISCV)] } {
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  set timing_lib $::env(RISCV)/cad/lib
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} else {
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  set timing_lib ../addins   
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}
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if {$tech == "sky130"} {
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    set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
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    lappend search_path $s8lib
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} elseif {$tech == "sky90"} {
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    set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
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    lappend search_path $s9lib
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} elseif {$tech == "tsmc28"} {
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    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
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    set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
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    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
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    lappend search_path $s10lib
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} elseif {$tech == "tsmc28psyn"} {
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    set TLU /home/jstine/TLU+
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    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
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    set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/    
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    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
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    lappend search_path $s10lib
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    set TLUPLUS true
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    set mw_logic1_net VDD
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    set mw_logic0_net VSS
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    set CAPTABLE $TLU/1p8m/
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    set MW_REFERENCE_LIBRARY /home/jstine/MW
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    set MW_TECH_FILE tcbn28hpcplusbwp30p140
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    set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus
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    set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
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    set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map
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}
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# Synthetic libraries
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set synthetic_library   [list dw_foundation.sldb]
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# Set standard cell libraries
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set target_library [list]
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#lappend target_library scc9gena_tt_1.2v_25C.db
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if {$tech == "sky130"} {
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    lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
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} elseif {$tech == "sky90"} {
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    lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
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} elseif {$tech == "tsmc28"} {
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    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
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} elseif {$tech == "tsmc28psyn"} {
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    set mw_reference_library [list ]    
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    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140    
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}
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# Set up DesignWare cache read and write directories to speed up compile.
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set cache_write  ~
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set cache_read   $cache_write
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# Tell DC where to look for files
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lappend search_path ./scripts
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lappend search_path ./hdl
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lappend search_path ./mapped
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if {($tech == "tsmc28psyn")} {
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    set memory /home/jstine/WallyMem/rv64gc/
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    set osumemory /import/yukari1/pdk/TSMC/WallyMem/rv64gc/    
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    lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
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    lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
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    lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
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    lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/ts1n28hpcpsvtb64x44m4sw
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/ts1n28hpcpsvtb64x128m4sw
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tsdn28hpcpa1024x68m4mw
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tsdn28hpcpa64x32m4mw
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}
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# Set Link Library
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set link_library "$target_library $synthetic_library"
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# Set up User Information
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set company "Oklahoma State University"
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set user    "James E. Stine"
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# Alias
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alias ra report_area
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alias rt report_timing
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alias rc {report_constraint -all_violators}
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alias sf set_flatten
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alias ss set_structure
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alias rco report_compile_options
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alias cs compile -scan
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alias csi compile -scan -incr -map high
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alias h history
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history keep 100
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alias all_gone {remove_design -designs}
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alias page_on {set sh_enable_page_mode true}
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alias page_off {set sh_enable_page_mode false}
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# specify directory for intermediate files from analyze
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define_design_lib DEFAULT -path ./analyzed
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# suppress Driving cell warning
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suppress_message {UID-401}
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########### Source Useful Tcl Procedures ###########
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foreach _file [glob -nocomplain ./tcl_procs/*.tcl] {
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  source $_file
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}
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############# Enable line editing in 2004.12 ###########
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set sh_enable_line_editing true
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############# Setup the view utility ###########
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proc view {args} {
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    redirect tmpfile1212 {uplevel $args}
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    # Without redirect, exec echos the PID of the new process to the screen
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    redirect /dev/null {exec ./tcl_procs/view.tk tmpfile1212 "$args" &}
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}
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alias vrt {view report_timing -nosplit}
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alias vrtm {view report_timing -nosplit -delay min}
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alias vman {view man}
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