mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
464 lines
23 KiB
Systemverilog
464 lines
23 KiB
Systemverilog
///////////////////////////////////////////
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// wallyTracer.sv
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//
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// A component of the Wally configurable RISC-V project.
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// Implements a RISC-V Verification Interface (RVVI)
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// to support functional coverage and lockstep simulation.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`define STD_LOG 0
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`define PRINT_PC_INSTR 0
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`define PRINT_MOST 0
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`define PRINT_ALL 0
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`define PRINT_CSRS 0
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// Since we are detecting the CSR change by comparing the old value, we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want to hold the old value.
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`define CONNECT_CSR(name, addr, val) \
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logic [P.XLEN-1:0] prev_csr_``name; \
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always_ff @(posedge clk) \
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prev_csr_``name <= rvvi.csr[0][0][addr]; \
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assign rvvi.csr_wb[0][0][addr] = (rvvi.csr[0][0][addr] != prev_csr_``name); \
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assign rvvi.csr[0][0][addr] = valid ? val : prev_csr_``name;
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module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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localparam NUM_REGS = P.E_SUPPORTED ? 16 : 32;
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localparam NUM_CSRS = 4096;
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// wally specific signals
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logic reset;
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logic clk;
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logic InstrValidD, InstrValidE;
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logic StallF, StallD;
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logic STATUS_SXL, STATUS_UXL;
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logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
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logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
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logic InstrValidM, InstrValidW;
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logic StallE, StallM, StallW;
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logic GatedStallW;
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logic SelHPTW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic TrapM, TrapW;
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logic HaltM, HaltW;
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logic [1:0] PrivilegeModeW;
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logic [P.XLEN-1:0] rf[NUM_REGS];
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logic [NUM_REGS-1:0] rf_wb;
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logic [4:0] rf_a3;
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logic rf_we3;
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logic [P.FLEN-1:0] frf[32];
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logic [31:0] frf_wb;
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logic [4:0] frf_a4;
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logic frf_we4;
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logic [P.XLEN-1:0] CSRArray [4095:0];
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logic [P.XLEN-1:0] CSRArrayOld [4095:0];
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logic [NUM_CSRS-1:0] CSR_W;
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logic CSRWriteM, CSRWriteW;
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logic [11:0] CSRAdrM, CSRAdrW;
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logic wfiM;
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logic InterruptM, InterruptW;
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logic valid;
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//For VM Verification
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logic [(P.XLEN-1):0] IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW;
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logic [(P.XLEN-1):0] IPTEF,IPTED,IPTEE,IPTEM,IPTEW,DPTEM,DPTEW;
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logic [(P.PA_BITS-1):0] IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW;
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logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW;
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logic [1:0] IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW;
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logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
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logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
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assign clk = testbench.dut.clk;
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// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
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assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
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assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE;
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assign InstrValidM = testbench.dut.core.ieu.InstrValidM;
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assign InstrRawD = testbench.dut.core.ifu.InstrRawD;
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assign PCNextF = testbench.dut.core.ifu.PCNextF;
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assign PCF = testbench.dut.core.ifu.PCF;
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assign PCD = testbench.dut.core.ifu.PCD;
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assign PCE = testbench.dut.core.ifu.PCE;
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assign PCM = testbench.dut.core.ifu.PCM;
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assign reset = testbench.reset;
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assign StallF = testbench.dut.core.StallF;
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assign StallD = testbench.dut.core.StallD;
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assign StallE = testbench.dut.core.StallE;
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assign StallM = testbench.dut.core.StallM;
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assign StallW = testbench.dut.core.StallW;
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assign GatedStallW = testbench.dut.core.lsu.GatedStallW;
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assign SelHPTW = testbench.dut.core.lsu.hptw.hptw.SelHPTW;
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assign FlushD = testbench.dut.core.FlushD;
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assign FlushE = testbench.dut.core.FlushE;
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assign FlushM = testbench.dut.core.FlushM;
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assign FlushW = testbench.dut.core.FlushW;
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assign TrapM = testbench.dut.core.TrapM;
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assign HaltM = testbench.DCacheFlushStart;
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if (P.ZICSR_SUPPORTED) begin
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assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
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assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
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assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
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assign wfiM = testbench.dut.core.priv.priv.wfiM;
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assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
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end else begin
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assign PrivilegeModeW = 2'b11;
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assign STATUS_SXL = 0;
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assign STATUS_UXL = 0;
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assign wfiM = 0;
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assign InterruptM = 0;
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end
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//For VM Verification
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assign IVAdrF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
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assign DVAdrM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
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assign IPAF = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
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assign DPAM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
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assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
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assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
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assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
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assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE;
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assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
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assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
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assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
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assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
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assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
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// CSR connections
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if (P.ZICSR_SUPPORTED) begin
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// M-mode trap CSRs
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`CONNECT_CSR(MSTATUS, 12'h300, testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW);
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`CONNECT_CSR(MEDELEG, 12'h302, testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW);
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`CONNECT_CSR(MIDELEG, 12'h303, testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
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`CONNECT_CSR(MIE, 12'h304, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW);
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`CONNECT_CSR(MTVEC, 12'h305, testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW);
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`CONNECT_CSR(MSCRATCH, 12'h340, testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW);
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`CONNECT_CSR(MEPC, 12'h341, testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW);
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`CONNECT_CSR(MCAUSE, 12'h342, testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW);
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`CONNECT_CSR(MTVAL, 12'h343, testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW);
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`CONNECT_CSR(MIP, 12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
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// S-mode trap CSRs
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`CONNECT_CSR(SSTATUS, 12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
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`CONNECT_CSR(SIE, 12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
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`CONNECT_CSR(STVEC, 12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
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`CONNECT_CSR(SSCRATCH, 12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
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`CONNECT_CSR(SEPC, 12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
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`CONNECT_CSR(SCAUSE, 12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
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`CONNECT_CSR(STVAL, 12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
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`CONNECT_CSR(SIP, 12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
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// Virtual Memory CSRs
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`CONNECT_CSR(SATP, 12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
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// Floating-Point CSRs
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`CONNECT_CSR(FFLAGS, 12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
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`CONNECT_CSR(FRM, 12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
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`CONNECT_CSR(FCSR, 12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
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// Counters / Performance Monitoring CSRs
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`CONNECT_CSR(MCOUNTEREN, 12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
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`CONNECT_CSR(SCOUNTEREN, 12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
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`CONNECT_CSR(MCOUNTINHIBIT, 12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
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// mhpmevent3-31 not connected (232-33F)
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`CONNECT_CSR(MCYCLE, 12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
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`CONNECT_CSR(MINSTRET, 12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
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// mhpmcounter3-31 not connected (B03-B1F)
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// cycle, time, instret not connected (C00-C02)
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// hpmcounter3-31 not connected (C03-C1F)
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// Machine Information Registers and Configuration CSRs
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`CONNECT_CSR(MISA, 12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
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`CONNECT_CSR(MENVCFG, 12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
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`CONNECT_CSR(SENVCFG, 12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
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`CONNECT_CSR(MSECCFG, 12'h747, 0); // mseccfg
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`CONNECT_CSR(MVENDORID, 12'hF11, 0); //mvendorid
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`CONNECT_CSR(MARCHID, 12'hF12, 0); // marchid
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`CONNECT_CSR(MIMPID, 12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
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`CONNECT_CSR(MHARTID, 12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
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`CONNECT_CSR(MCONFIGPTR, 12'hF15, 0); //mconfigptr
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// Sstc CSRs
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`CONNECT_CSR(STIMECMP, 12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
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// Zkr CSRs
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// seed not connected (015)
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// extra CSRs for RV32
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if (P.XLEN == 32) begin
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`CONNECT_CSR(MSTATUSH, 12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
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`CONNECT_CSR(MENVCFGH, 12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
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`CONNECT_CSR(MSECCFGH, 12'h757, 0); // mseccfgh
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`CONNECT_CSR(STIMECMPH, 12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
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end
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end
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// PMP CSRs
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if (P.PMP_ENTRIES > 0) begin
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always_comb begin
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if(valid) begin
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// PMPCFG CSRs (space is 0-15 3a0 - 3af)
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localparam inc = P.XLEN == 32 ? 4 : 8;
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int i, i4, csrid;
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logic [P.XLEN-1:0] pmp;
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for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
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i4 = i / 4;
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csrid = 12'h3A0 + i4;
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pmp = 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+0] << 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+1] << 8;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+2] << 16;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+3] << 24;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+4] << 32;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+5] << 40;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+6] << 48;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+7] << 56;
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CSRArray[csrid] = pmp;
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end
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// PMPADDR CSRs (space is 0-63 3b0 - 3ef)
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for (i=0; i<P.PMP_ENTRIES; i++) begin
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csrid = 12'h3B0 + i;;
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pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
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CSRArray[csrid] = pmp;
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end
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end else begin // hold the old value if the pipeline is stalled.
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// PMP CFG 3A0 to 3AF
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int csrid;
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for(csrid='h3A0; csrid<='h3AF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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// PMP ADDR 3B0 to 3EF
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for(csrid='h3B0; csrid<='h3EF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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end
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end
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end
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// record previous csr value.
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always_ff @(posedge clk) begin
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int csrid;
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// PMP CFG 3A0 to 3AF
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for(csrid='h3A0; csrid<='h3AF; csrid++)
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CSRArrayOld[csrid] = CSRArray[csrid];
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// PMP ADDR 3B0 to 3EF
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for(csrid='h3B0; csrid<='h3EF; csrid++)
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CSRArrayOld[csrid] = CSRArray[csrid];
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end
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// PMP CFG 3A0 to 3AF
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genvar index;
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for(index='h3A0; index<='h3AF; index++) begin
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assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
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assign rvvi.csr_wb[0][0][index] = CSR_W[index];
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assign rvvi.csr[0][0][index] = CSRArray[index];
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end
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// PMP ADDR 3B0 to 3EF
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for(index='h3B0; index<='h3EF; index++) begin
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assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
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assign rvvi.csr_wb[0][0][index] = CSR_W[index];
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assign rvvi.csr[0][0][index] = CSRArray[index];
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end
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// Integer register file
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assign rf[0] = 0;
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for(index = 1; index < NUM_REGS; index += 1)
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assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
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assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3;
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assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3;
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always_comb begin
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rf_wb <= 0;
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if(rf_we3)
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rf_wb[rf_a3] <= 1'b1;
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end
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// Floating-point register file
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if (P.F_SUPPORTED) begin
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assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
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assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
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for(index = 0; index < 32; index += 1)
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assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
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end else begin
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assign frf_a4 = '0;
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assign frf_we4 = 0;
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for(index = 0; index < 32; index += 1)
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assign frf[index] = '0;
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end
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always_comb begin
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frf_wb <= 0;
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if(frf_we4)
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frf_wb[frf_a4] <= 1'b1;
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end
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// CSR writes
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assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM;
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assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
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// pipeline to writeback stage
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flopenrc #(32) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
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flopenrc #(32) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
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flopenrc #(32) InstrRawWReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrRawM, InstrRawW);
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flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW & ~TrapM, ~StallW, PCM, PCW);
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flopenrc #(1) InstrValidMReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrValidM, InstrValidW);
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flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
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flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW);
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flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
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flopenrc #(12) CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW);
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flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
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//for VM Verification
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flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
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flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU
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flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU
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flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
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flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU
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flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU
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flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
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flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU
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flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU
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flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
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flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU
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flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU
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flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
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flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU
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flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU
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flopenrc #(P.PPN_BITS) IPPNMReg (clk, reset, 1'b0, ~StallM, IPPNE, IPPNM); //Physical Page Number for IMMU
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flopenrc #(P.PPN_BITS) IPPNWReg (clk, reset, 1'b0, ~StallW, IPPNM, IPPNW); //Physical Page Number for IMMU
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flopenrc #(P.PPN_BITS) DPPNWReg (clk, reset, 1'b0, ~StallW, DPPNM, DPPNW); //Physical Page Number for DMMU
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flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess
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flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess
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flopenrc #(1) ExecuteAccessDReg (clk, reset, 1'b0, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access
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flopenrc #(1) ExecuteAccessEReg (clk, reset, 1'b0, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access
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flopenrc #(1) ExecuteAccessMReg (clk, reset, 1'b0, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access
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flopenrc #(1) ExecuteAccessWReg (clk, reset, 1'b0, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access
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// Initially connecting the writeback stage signals, but may need to use M stage
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// and gate on ~FlushW.
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assign valid = ((InstrValidW | TrapW) & ~StallW) & ~reset;
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assign rvvi.clk = clk;
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assign rvvi.valid[0][0] = valid;
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assign rvvi.order[0][0] = rvvi.csr[0][0][12'hB02]; // TODO: IMPERAS Should be event order
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assign rvvi.insn[0][0] = InstrRawW;
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assign rvvi.pc_rdata[0][0] = PCW;
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assign rvvi.trap[0][0] = TrapW;
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assign rvvi.halt[0][0] = HaltW;
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assign rvvi.intr[0][0] = InterruptW;
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assign rvvi.mode[0][0] = PrivilegeModeW;
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assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
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PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
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assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM :
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~FlushM ? PCE :
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~FlushE ? PCD :
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~FlushD ? PCF : PCNextF;
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for(index = 0; index < NUM_REGS; index += 1) begin
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assign rvvi.x_wdata[0][0][index] = rf[index];
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assign rvvi.x_wb[0][0][index] = rf_wb[index];
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end
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for(index = 0; index < 32; index += 1) begin
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assign rvvi.f_wdata[0][0][index] = frf[index];
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assign rvvi.f_wb[0][0][index] = frf_wb[index];
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end
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// *** implementation only cancel? so sc does not clear?
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assign rvvi.lrsc_cancel[0][0] = 0;
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integer index2;
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string instrWName;
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int file;
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string LogFile;
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if(`STD_LOG) begin
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instrNameDecTB #(P.XLEN) NameDecoder(rvvi.insn[0][0], instrWName);
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initial begin
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LogFile = "logs/boottrace.log";
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file = $fopen(LogFile, "w");
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end
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end
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always_ff @(posedge clk) begin
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if(valid) begin
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if(`STD_LOG) begin
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$fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
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for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
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if(rvvi.x_wb[0][0][index2]) begin
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$fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
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end
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end
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end
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for(index2 = 0; index2 < 32; index2 += 1) begin
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if(rvvi.f_wb[0][0][index2]) begin
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$fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
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end
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end
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for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
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if(rvvi.csr_wb[0][0][index2]) begin
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$fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
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end
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end
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$fwrite(file, "\n");
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if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
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$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
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else if(`PRINT_MOST & !`PRINT_ALL)
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$display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x",
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rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
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else if(`PRINT_ALL) begin
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$display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x",
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rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
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for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
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$display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
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end
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for(index2 = 0; index2 < 32; index2 += 1) begin
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$display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
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end
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end
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if (`PRINT_CSRS) begin
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for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
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if((rvvi.csr[0][0][index2] != CSRArrayOld[index2])) begin
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$display("%t: CSR %03x = %x", $time(), index2, rvvi.csr[0][0][index2]);
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end
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end
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end
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end
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if(HaltW) $finish;
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end
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endmodule
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