cvw/tests/coverage
2024-01-10 10:01:46 -08:00
..
csrwrites.S Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
dcache1.py Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 2023-04-19 01:34:01 -07:00
dcache1.S Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 2023-04-19 01:34:01 -07:00
dcache2.S add D$ test case to trigger a FlushStage while SetDirtyWay=1 2023-04-19 01:34:01 -07:00
ebu.S
fpu.S Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
ieu.S Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
ifu.S Added Zcb c.lbu coverage test 2024-01-10 10:01:46 -08:00
ifuCamlineWrite.S
lsu.S
Makefile Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
pmp.S
pmpadrdecs.S Pmpadrdecs test cases changing AdrMode to 2 or 3 2023-04-27 12:23:35 -07:00
pmpcfg1.S
pmpcfg2.S
pmpcfg.S pmpaddr0 and pmpaddr2 test cases 2023-04-25 15:37:04 -07:00
pmppriority.S added tests for pmppriority module 2023-04-27 16:12:43 -07:00
priv.S Merge pull request #394 from harshinisrinath1001/main 2023-08-24 19:16:50 -07:00
tlbASID.S Update tlbASID.S 2023-04-27 14:32:57 -07:00
tlbGLB.S Comment tlbGBL more discriptively 2023-05-04 19:13:47 -05:00
tlbGP.S complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
tlbKP.S
tlbM3.S Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
tlbmisc.S Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate 2024-01-05 22:45:15 -08:00
tlbMP.S complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
tlbNAPOT.S Updated tlbNAPOT to test instructions as well 2023-12-20 23:01:35 -08:00
tlbTP.S complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
vm64check.S
WALLY-init-lib.h Improved NAPOT test coverage 2023-08-30 21:04:36 -07:00