kipmacsaigoren 8e35701103 Merging new changes into the old one's I've made in the OKstate servers		2021-10-08 17:47:11 -05:00
..
adrdec.sv	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
adrdecs.sv	Fixed adrdecs to use Access signals for TIMs	2021-07-05 23:42:58 -04:00
decoder.sv	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
hptw.sv	Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR	2021-09-03 10:26:38 -05:00
mmu.sv	partial dcache reorg.	2021-08-25 12:42:05 -05:00
pmachecker.sv	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00
pmpadrdec.sv	removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.	2021-10-08 15:33:18 -07:00
pmpchecker.sv	removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.	2021-10-08 15:33:18 -07:00
priorityonehot.sv	changed priority circuits for synthesis and light cleanup	2021-09-15 12:24:24 -05:00
prioritythermometer.sv	changed priority circuits for synthesis and light cleanup	2021-09-15 12:24:24 -05:00
tlb.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:39:07 -05:00
tlbcam.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbcamline.sv	Fixed TLB parameterization and valid bit flop to correctly do instr page faults	2021-07-21 14:44:43 -04:00
tlbcontrol.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:44:32 -05:00
tlblru.sv	Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's	2021-07-23 11:57:58 -05:00
tlbmixer.sv	Broken.	2021-07-19 10:33:27 -05:00
tlbram.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbramline.sv	Eliminate reserved bits from TLB RAM	2021-07-08 17:35:00 -04:00